Flexible Power-Up Sequencing For LCDs

July 1, 2005
Bart Borosky looks at how a programmable, precision power-management circuit meets power-up needs for multiple vendor LCDs.

For many systems, LCDs are a large part of the bill of materials (BOM). In some cases, such as HDTVs, more than 80% of the entire system cost is that of the LCD panel. From a perceived quality perspective, if the LCD begins to fail, the end customer will associate the system and its manufacturer with poor quality. Clearly, safeguarding the LCD component is a critical aspect of these system designs.

LCDs are typically comprised of a liquid-crystal fluid sandwiched between two polarizing layers of glass or plastic, separated into cells (pixels). For colour LCDs, each pixel is divided into three sub-cells—red, blue, and green. When a voltage is applied across these LCD sub-cells, a certain amount of light passes through the LCD cell from the backlight or reflective surface, depending on the voltage applied and polarisation of the liquid-crystal fluid.

In order for the LCD to operate reliably, the liquid-crystal fluid must be protected from the DC voltages (typically negative) that cause breakdown. If too much DC current inadvertently flows through the LCD fluid, the fluid will become damaged, electrochemically decomposing and breaking down over time as the fluid changes state.

PREVENTING LCD BREAK DOWN To prevent any damaging DC current, some LCDs have an "M" clock that, when activated at power-up, produces an AC current wave on the electrodes and into the fluid cells before the display "comes to life." This protects the cells from breakdown. Many LCDs have built-in controllers that need DC logic signals on power-up. Care must be taken in the order and timing of how power is applied to the LCD. If the data signals come in either before or too long after VCC power-up, latch-up, or damage to the LCD cells can occur. Similarly, at power-down, removal of VCC is usually delayed until the logic and data signals have been turned off. All LCDs have power-up sequencing requirements of some type. The key is to make sure that the LCD fluid is protected from DC voltages without the AC wave being set up, within the requirements provided by the LCD vendor. Each LCD vendor has different power-up and power-down sequencing requirements, varying by the LCD model. A basic power-up sequence for a popular 18in. TFT LCD is shown in Figure 1.

Single system support for multiple LCD vendors can be extremely beneficial. Multi-vendor competition often leads to price reductions of 10% or more. In addition, if an LCD vendor decides to obsolete a particular LCD, and the design supports multiple vendors, the design will easily accommodate the switch to another vendor.

PROTECTION FROM FAULTY POWER SUPPLIES The focus so far has been on power-up sequencing requirements for the LCD, with the assumption that the power supply is operating correctly. In this case of a faulty power supply, the LCD needs protection from any damage caused. This is accomplished by ensuring that the unwanted DC current is not pumped into the LCD fluid. The end customer will find a minor repair for a faulty power supply more tolerable—and less damaging to the manufacturer's reputation—than a complete LCD replacement.

To protect the LCD from a faulty power supply, a circuit is required that senses the correct operation of the power supply and only then supplies DC to the LCD controller in the proper sequence for a particular LCD.

INTEGRATING ADDITIONAL POWER-UP CIRCUITRY Power-up circuitry to protect the LCD from both unwanted DC at power-up and faulty power supplies can be complex, requiring several analog and digital components. Since the system design will require power-up and faulty power-supply protection of some type, it would be preferable to be able to reuse some or all of this circuitry for additional portions of the system. A number of common system chips (e.g., ASICs, DSPs, ASSPs, FPGAs, and microprocessors), many of which comprise much of the overall system cost, also have power-up sequencing and timing requirements.

Coordinating the power-up of the I/O and core supply voltages and protecting these chips, in conjunction with the LCD, would be yet another important aspect of the system design. To further complicate matters, some of these chips might require their highest voltage to be turned on prior to their lowest voltage, or vice versa, and require the reverse for power-down.

In most cases, however, protecting two different chips or two different LCDs require completely different power-up circuits, different design, and more components.

This combination of multiple, complex power-up requirements begs for a simple solution. Lattice Semiconductor's programmable precision power-management device satisfies many of the requirements for complex power-up sequencing and monitoring for LCD systems. The Power1208P1 chip is a combination of analog and digital circuitry (Fig. 2).

The analog portion of the device consists of programmable power-supply monitor inputs and high-voltage FET outputs. The power-supply voltage monitors are arranged as 12 independent comparators, each with 384 programmable trip point settings. All 12 input comparators can be monitored simultaneously and feature variable hysteresis that scales with the voltage being monitored.

The analog output portion of the device consists of four high-voltage N-channel MOSFET drivers, which have individually controllable charge current (0.5µA to 50µA), and maximum voltage (8V to 12V) gate drivers.

The digital logic portion of the device consists of four digital inputs, a 16-macrocell CPLD and four digital outputs, which are labeled "digital signal monitor," "CPLD" and "programmable function digital output" in Figure 2. Simply put, the digital logic portion of the device is able to take the analog and digital inputs, and comparator outputs, and process these signals via programmable logic, and control the analog and digital outputs of the device to perform sequencing and monitoring functions.

The CPLD architecture is an array of AND, OR, XOR gates, multiplexers, flip-flops, and feedback paths, structured into programmable blocks called macrocells, along with programmable routing that allows the blocks to be interconnected to perform specific logic functions.

The CPLD in the Power1208P1 is based on the industry-standard ispMACH architecture, which is robust and facilitates glitch protection.

The final section of the Power1208P1 device is a programmable timer, called "internal oscillator and timers" in Figure 2, that can be used for sequence delays and watchdog timers. There are four embedded programmable timers that interface with the CPLD, along with an internal programmable oscillator.

The CPLD clock can be programmed with eight different frequencies based on the internal oscillator frequency of 250kHz, with a frequency divider from 1 to 128 in eight ratios.

PROGRAMMABLE POWER MANAGER By connecting the analog inputs of the Power1208P1 to a few external signals for monitoring, such as LVDS logic present, Vcc OK, and Vcc>Vt, the comparator outputs can control internal digital CPLD logic that will sequence the analog and digital outputs of the device.

As shown in Figure 3, the Power1208P1 device controls the required signals for LCD power-up sequencing and monitoring of the power supply and LVDS data. If a faulty power-supply condition is present, the LVDS data will not damage the LCD and no logic DC levels will enter the LCD crystal fluid. Also, as shown, additional logic, inputs, and outputs for the Power1208P1 can be used to control power-up sequencing requirements for other logic circuitry, such as the DSP or microprocessor.

The Power1208P1 is programmed using a GUI-driven software environment called PAC-Designer, as shown in Figure 4. Each analog input can be individually setup via a pulldown menu, setting threshold values for monitoring each analog input. To define sequences and conditions to monitor, the CPLD logic portion of the design is typically done using a series of pulldown menus called LogiBuilder, or, for extended functionality, ABEL design entry for combinatorial and state-machine design.

Once the device is designed using the PAC-Designer software, the design is then compiled into a JEDEC file that contains the "fusemap" for the device. Lattice's Power1208P1 device fuses are based on E2CMOS technology, and can be programmed and reprogrammed "in-system" via the JTAG port of the device. All that's required for reprogramming is a new JEDEC file. If the LCD vendor changes specifications after the device is installed, the system can be reprogrammed via the Internet after it has shipped to the end customer. The customer (or service technician) simply downloads a new driver and uploads the revised JEDEC file into the Power1208P1.

In summary, programmable power-management devices can be used to simplify power management and sequencing for multiple LCDs and offload additional power-up tasks such as logic circuitry. Instead of using multiple analog and digital devices, the Power1208P1 solution can be used for power sequencing and management of not only the LCD, but also other logic circuitry such as the DSP and microprocessor. Since power-up management can be integrated into one programmable design platform, the benefit to the designer is clear: The device can be reprogrammed during manufacturing to support multiple display vendors.


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