As Figure A shows, data is written into the device using the data inputs (Din), write clock (WCLK), and write enable (WEN). A queue is selected using the write address bus (WRADD), the rising edge of the WCLK, and write address enable (WADEN). Each queue is selected on a single WCLK cycle. Because the write port is designed to achieve 100% bus usage, data can be written into the device on every WCLK rising edge, including the cycle that a new queue is addressing.
Once a queue is selected, all subsequent writes are written to that queue until a new queue is selected. A minimum of three clock cycles must occur between queue selections on the write port. On the next WCLK rising edge, the write port discrete full flag will update to display the full status of the newly selected queue. On the second rising edge of WCLK, data present on the data input bus (Din) can be written into the newly selected queue as long as WEN is Low and the new queue isn’t full. If the newly selected queue is full, the device will prevent writes to that queue.
Refer to Figure B for read operations. Each queue is read from a common read port using the data outputs (Qout), read clock (RCLK), and read enable (REN). A queue is selected using the read address bus (RDADD), the rising edge of RCLK, and read address enable (RADEN). A queue is selected for reading in a single cycle; all following reads will be read from the selected queue until a new queue is selected.
A minimum of three RCLK cycles must occur between queue selections on the read port. Data can
still be read from the previously selected queue on the same RCLK rising edge that the new queue is selected if REN is Low active and the previous queue isn’t empty. A fall-through operation directs the device to read a word from the previously selected queue, regardless of REN, on the following rising edge of RCLK. Once a queue is selected on the read port, the next word available in that queue will fall through to the output register as long as the queue isn’t empty.
