Embedded Design Challenges Hold Center Stage At 39th DAC

June 10, 2002
Picking up where last year’s show left off, the Design Automation Conference brings a wealth of technical information for embedded-system designers.

The best technical conferences are planned with an eye on real-life design challenges. With embedded systems foremost in the minds of legions of design engineers, the 39th Design Automation Conference (DAC, June 10-14, New Orleans) takes its cues from embedded electronics, which pervade almost every aspect of our daily lives.

At this year's DAC, some 15,000 attendees will hear presentations of over 160 technical papers. The second annual Embedded Systems Showcase offers exhibitors and attendees a highly focused area to display and view tools for the design of embedded systems-on-a-chip (SoCs). Over 225 EDA, silicon, embedded software, and hardware vendors will be on hand.

In addition to the embedded-systems emphasis in the technical program, a track called Design Methods Sessions covers a wide range of methodology-oriented topics. Many sessions also are geared toward embedded-system design.

DAC's program committee has revamped its Monday schedule, making June 10 a don't-miss day. Among the events are a full-day tutorial on issues and problems related to embedded-system software design. A morning-long hands-on tutorial covers development of bus-functional models for embedded ATM switch verification, while an afternoon hands-on session tackles the creation and use of virtual prototypes for embedded-system verification.

This year's hands-on tutorials are a new feature to the conference. The in-depth, interactive sessions will allow participants to work with the tools. Sessions address many embedded-systems design challenges, from system verification and assertion-based validation, to hardware/software integration and virtual prototyping. In keeping with DAC's embedded-systems focus, the theme of the hands-on tutorials is "Verifying Embedded Systems."

Tutorials in general are a big focus this year at DAC. Five will take place on Friday, June 15, with topics ranging from intellectual property (IP) design and integration for SoCs, modeling technology for high-frequency design, using System C for high-level modeling and design, best practice for physical chip implementation, and new computing platforms for embedded systems.

The opening session and keynote will be delivered on Tuesday, June 11 by Hajime Sasaki, chairman at NEC Corp. Sasaki will outline a paradigm shift in which the design process itself has become the key to the semiconductor industry's future success. He'll address the changes necessary to the traditional design hierarchy and the need for a revolution in functional design.

A second keynote address comes from Jerry Fiddler, chairman of Wind River Systems, on the afternoon of Thursday, June 13. Fiddler's topic is the melding of the traditionally distinct realms of embedded software, silicon manufacturing, and electronic design automation. Despite earlier failed efforts to bring these disparate worlds into harmony, Fiddler contends that now is the time to bridge the gaps.

Workshops are a continuing tradition at DAC as well. The fifth annual "Workshop for Women in Design Automation," a full-day interactive seminar focused on career advancement for women in the electronics industry, will be held Monday, June 10. Chris King, AMI Semiconductor's CEO, will give a keynote address.

A second Monday workshop of interest is the Interoperability Workshop. There, two panels will discuss both tool users' and the industry's views of progress in tool interoperability and what the future may hold. Since last year's DAC, the OpenAccess Coalition has made strides toward establishing an open and standard application programming interface (API). This workshop offers attendees a chance to learn more about its prospects for success.

Among the many sessions of interest to embedded designers, a few stand out. First up in the Design Methods track is Session 3, "Design Innovations for Embedded Processors." It details a number of innovations surrounding the design of these now-ubiquitous processors, including a technique for mixing compiled-code and interpreted-code approaches to instruction-set simulation.

Panel sessions are always interesting at DAC, and Session 31 comprises a panel that should draw a sizable crowd. Titled "Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible, Or Mission Irrelevant," the panel's chair, Gary Smith of Gartner Dataquest, will lead a group of experts through a discussion that picks up where Gerry Fiddler's keynote address leaves off. Is hardware-software co-design feasible for embedded systems, and is it even desirable?

For the many designers interested in the challenges of timing analysis and memory optimization for embedded systems, Session 40 is a must. It will introduce techniques such as a "schedulability" analysis algorithm for real-time systems.

Of course, not all DAC attendees have embedded-system design uppermost in their minds. Behavioral synthesis is a controversial topic that holds the promise of improved productivity for SoC designers. Session 55 will cover some of the latest advances in this technology, including how to bridge the gap between behavioral synthesis and processor design using state-of-the-art synthesis techniques.

Analog modeling will be addressed in Session 35, which tackles a number of subjects, including a high-level behavioral model of coupled oscillators. This paper, incidentally, is a candidate for DAC's annual Best Paper award. Another presentation in this session explores the application of formal verification to analog models, while a third discusses techniques for analyzing unsolvable systems that can be constructed using the VHDL-AMS hardware description language.

Several sessions address back-end implementation issues as well. Session 5, titled "New Perspectives in Physical Design," looks at some of the emerging trends in the back-end flow. Here attendees can hear another Best Paper candidate on the topic of uncertainty-aware circuit optimization, an approach to solving the problems related to transistor sizing.

Also of interest to users of back-end tools will be Special Session 46, titled "Designing SoCs for Yield Improvement." One presentation will explore the matter of so-called "infrastructure IP," an emerging technique that in-volves the embedding of special IP blocks that can help make SoCs more manufacturable.

A number of panel discussions on tap are sure to be lively. Session 22, titled "Whither (Or Wither?) ASIC Handoff?" will bring up the topic of ASIC handoff, exploring the future relationship between designers and their ASIC vendors.

There's plenty of interest out on the show floor at this year's DAC as well. When you've had your fill of technical sessions, panels, and workshops, the exhibits and demo suites will be buzzing with activity as vendors show off the latest EDA tools, including the following:

Analog Design: Analog designers are desperately in need of a productivity boost. DAC will see the debut of two powerful next-generation analog synthesis tools.

Being shown for the first time are the first two members of Analog Design Automation's (ADA's) Genius family. The Genius tools for analog, mixed-signal, and digital SoCs are based on ADA's intelligent systems algorithms. They've been integrated into both the Cadence and Mentor Graphics analog design flows (Fig. 1).

One of the new offerings, Creative Genius, creates entire databases of optimized analog and mixed-signal IP. The intelligent systems algorithms consider a raft of parameters simultaneously, and create all possible solutions that could meet specified design objectives, including design corners. Pricing starts at $80,000.

Also new, IP Explorer Genius enables users to evaluate solutions and performance tradeoffs by displaying an N-dimensional color graph (with N being the number of objectives the designer has specified). Prices begin at $38,000.

A second vendor of analog tools, Barcelona Design, will show its Prado synthesis platform and the first of its analog circuit IP engines, the Miro Class CGS18T phase-locked loop (PLL) clocking engine. Barcelona's approach to analog synthesis combines synthesizable circuit engines with the overall platform. Each engine provides function-, topology-, and process-specific models that enable accurate and very fast synthesis of custom analog circuits.

ASIC Synthesis: Okay, so digital designers need productivity too. At DAC, Synplicity will unveil version 2.3 of Synplify ASIC with MultiPoint synthesis technology. Aimed at large SoC designs, the technology uses incremental design techniques that enable parts of a design to remain unchanged while others are synthesized. It can optimize across design partitions too. Also new in Synplify 2.3 is the ability to perform set case analysis. Users can define different operating states for the design while the tool optimizes timing for each of them. One-year licenses will sell for $69,000.

Verification: Everyone wants to see the "verification bottleneck" busted open. On the formal verification side, Verplex Systems will show its latest suite of tools. The flow features new algorithms that will enable it to attack RTL-to-layout comparisons and complex arithmetic operators in compiled datapath logic, both with tighter integration to the transistor level. New capabilities let the tools handle previously unsolvable problems for formal tools, such as memory, compiled datapath, memory control, IP cores, complex I/O, and full custom logic.

Efficiency in the verification process is critical as ASIC gate counts rise. Axis Systems will show its Xtreme-II verification system, which simultaneously simulates, accelerates, and emulates SoC designs of up to 100 million gates. The system can reuse models at any level of abstraction—behavioral, RTL, gate, and discrete hardware model components—throughout the verification process, whether designers are in simulation, acceleration, or emulation modes, or any combination.

Emulation is an important part of SoC verification cycles. To that end, TransEDA is unveiling its VN-Cover Emulator to provide seamless coverage between simulation and emulation. It offers an objective measure of how well a design has been emulated and which parts have been under-emulated. The Emulator works with the Quickturn CoBALT and CoBALT Plus hardware platforms and Axis' Xcite and Xtreme verification systems. Pricing starts at $50,000.

TransEDA will also display the next release of its VN-Property DX dynamic property checker with the industry's first graphical property capture, viewing, and animating capability. With this latest release, users won't have to learn a new property language. A point-and-click on the interface lets them capture very complex properties.

Functional verification is only as good as the testbenches used to exercise the design. With the release of OpenVera 2.0, Synopsys provides one common language for writing assertions and formal properties. OpenVera 2.0 adds assertions that can be checked dynamically during simulation, and targeted for proofs by formal analysis tools. It also adds Intel's ForSpec language, which supplies language features for formal and hierarchical verification.

Post-layout, transistor-level verification of large SoC designs has historically been limited by the capacity of extraction tools. Celestry Design Technologies is debuting a complete, hierarchical extraction-to-hierarchical simulation flow for silicon-accurate signoff. These tools extract a complete, full-chip netlist, including RC parasitics, which is subsequently reduced and simulated hierarchically.

Another entry into the post-layout verification arena is Nassda's LEXSIM, a full-chip, circuit-level emulator. The tool performs dynamic power-network simulation to find and fix complex nanometer effects such as dynamic voltage (IR) drop. With so much less headroom in low-voltage designs, tools such as LEXSIM are critical in predicting IR drop-related problems. Pricing starts at $180,000 for time-based licenses.

Analysis Tools: As part of its NanoCool low-voltage design initiative, Sequence Design will offer enhancements to two tools at DAC. PowerTheatre, which performs power analysis at the architectural level as well as RTL power optimization, now includes vectorless power analysis and SoC power modeling. The former enables upfront power analysis at the chip level without modeling, while designers can employ the latter to create detailed power models for IP blocks. One-year licensing costs $80,000.

Sequence's PhysicalStudio, for concurrent optimization of chip timing and signal integrity, now offers the ability to control threshold voltage at individual transistors to account for power leakage. The next release will also include analysis and optimization of electromigration and hot-electron effects in standard cell-based design. One-year licensing goes for $175,000.

Real Intent is announcing the addition of an assertion-based clock domain analysis capability to Verix. This feature offers analysis and formal verification of asynchronous interfaces in designs, as well as formal analysis for reliable clocking of synchronous designs.

On the RTL analysis front, Atrenta's SpyGlass SoC addresses the logical issues that designers confront when integrating IP from various sources. The tool creates a logical virtual prototype to help predict and eliminate problems in the HDL code. It performs both coding and structural analysis during the RTL design phase to address key SoC integration issues including clocking, verification, reuse, emulation, and testability. Prices start at $60,000 per year.

Another RTL analysis tool that looks ahead to implementation will be InTime Software's Time Planner. Billed as a design planning system, the product generates a physical floorplan directly from RTL, maintaining logical hierarchy and generating synthesis constraints to expedite runs. Prices start at $98,000 for time-based licenses.

Embedded memory is a subject of growing interest to SoC designers. SynTest is launching its TurboDebug-SoC/Memory tool, which gives users a means of debugging BISTed memory blocks ahead of production by diagnosing and locating memory faults in a pc-board prototype. Using the 1149.1 JTAG interface for communication between the PC and the chip under test, the tool annotates debug results on design schematics.

Pc-Board Tools: Cadence is showing the latest release of its pc-board design tools, with enhancements to both its Studio and Expert series flows. Of particular interest is the ability to measure differential signaling for die-to-die interconnect across both IC packages and pc boards (Fig. 2). Now incorporated in the SPECCTRAQuest design and analysis package, this technology allows users to simulate differential signals as a unit in pre- and post-layout simulations. A one-year license runs $24,200 and up.

A complete front-to-back, high-speed pc-board design system will be announced by Innoveda. The package, called Innoveda HSD, will cover all phases of pc-board design from definition to physical design to verification. Two specialized tool suites, DxDesigner HSD and PowerPCB HSD, target electrical engineers and pc-board designers, respectively. Pricing will be in the $100,000 range with availability arriving this summer.

Physical IC Design: New and tighter design rules demand a lot of IC routers. Plato Design Systems will show its NanoRoute-SI router for high-end SoCs at 0.13 µm and below. The tool performs routing and physical optimization concurrently, giving users a fast road to timing closure. It relies on Plato's graph-based routing engine, which eschews wireload models in favor of real physical optimization.

Cadence is unveiling broad upgrades to its synthesis/place-and-route flow at DAC. Changes include enhancements to BuildGates synthesis, Physically Knowledgeable Synthesis (PKS), and the Silicon Ensemble and SOC Encounter place-and-route systems. PKS will offer tight timing correlation and high capacity for rapid timing closure. Plus, a next-generation tool provides flexibility and productivity in power planning and routing. An embedded signal-integrity tool set grants crosstalk analysis and timing-driven post-route repair.

As process technology moves farther ahead, foundries release new design rules that see numerous minor tweaks. This produces a gap between the capabilities of designers' physical layout tools and the latest set of rules. Sagantec's SiFix tool automatically corrects and optimizes physical IC designs, relieving designers from design-rule complexity and the implementation of preferred rules (Fig. 3).

Design Languages: Look for a number of announcements at DAC related to high-level design languages, including Co-Design Automation's Superlog and SystemVerilog. Accellera is expected to announce the release of its awaited SystemVerilog standard just before the show kicks off. We should see some related vendor announcements regarding products.

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