With system-on-a-chip (SoC) process geometries shrinking below 100 nm and supply voltages falling to 1 V and less, dynamic full-chip power integrity becomes harder to verify and achieve. Apache's Tomahawk-SDL takes on power-grid design and verification on a full-chip scale. Its vectorless analysis technique computes the worst-case switching scenarios and event sequence for peak IR drop without need for a VCD file from the designer.
Verification of simultaneous switching issues is more difficult than ever at smaller geometries. "They're not simply frequency-related," says Keith Mueller, Apache's VP of marketing. "There are dynamic issues that can't be caught by static tools." Static IR drop is relatively easy to probe and control, but dynamic effects aren't so readily determined.
Tomahawk-SDL quickly identifies and analyzes dynamic "hot spots" on an SoC early in design. In doing so, it accounts not only for worst-case simultaneous switching, but also for package parasitics and on-chip decoupling capacitances. These often are inserted throughout an SoC design in an ad hoc fashion.
The tool visually displays both the hot spots and the distribution of decoupling capacitors. It accounts for inherent capacitance as well as the decoupling added by designers. Users can then optimize power-ground distribution for best-case current consumption. The tool also supports extensive "what if" analyses.
The tool bases its vectorless analysis on comprehensive transistor-level power libraries. The full cell library used on a design is characterized using the design-specific loading, slews, and other parameters to capture accurate transient current waveforms and power data.
Tomahawk-SDL can process an average 4 million-gate SoC in less than two hours for both full-chip static and dynamic IR-drop analysis. It runs on Linux, Sun Solaris, and HP-UX platforms. Beta testing is in progress. Production release is scheduled for April 30. A one-year license starts at $160,000.
Apache Design Solutions
www.apache-da.com
