Environment Speeds Platform-Based SoC Design And Verification
Getting the most from system-on-a-chip (SoC) designs requires optimal design of the logic surrounding the embedded processor. As SoCs have increased in complexity, optimizing the interfaces between the processor and its peripherals has become a tedious design step. Now, a new design environment lets design teams build and configure an SoC core and its corresponding peripherals and software in a virtual prototype.
The Platform Express environment from Mentor Graphics generates a custom verification environment to verify interfaces in the portion of the design surrounding the embedded processor and its attached peripherals. By automating tedious and error-prone design creation and verification steps, Platform Express shortens product development cycles and allows designers to focus on product differentiators.
To assist design groups, processor vendors are beginning to supply configurable designs (core platforms). These include memory and many common peripherals optimized for use with the processor core, as well as some standard connection ports. Additional user-designed logic can be quickly added to these ports. Using Platform Express, designers can browse through a library of available processors, memories, and peripherals and drag and drop selected items into a graphical editor.
The environment provides a graphical user interface that enables users to create systems as block diagrams. It also automatically creates the necessary connections between components, depending on a selection of standard buses, including AMBA and VCI. A memory map display that automatically displays utilization of address space is included as well.
The platform-based design methodology supported by Platform Express not only generates complete hardware and software SoC designs, it also generates custom execution environments required to verify designs (see the figure). Each set of verification tools customized for a particular design is called an execution environment. Most design groups require multiple execution environments to complete the verification of a design's hardware and software. Each environment will support a different combination of tools and verification targets while offering different levels of accuracy and performance.
Once graphical entry is complete, Platform Express automatically generates the design, as well as the software to run on the design and a test bench to drive it. Platform Express then invokes verification tools, transparently generating and executing scripts that would be time-consuming to prepare manually. It also automatically generates diagnostic code for each peripheral and memory component in the design. Designers can proceed to hardware/software coverification using the Seamless coverification tool or to RTL-level hardware verification using the ModelSim tool.
The company is collaborating with leading semiconductor firms to offer Platform Express design kits for popular SoC platforms. The first platform developers include Oki Semiconductor and Altera Corp. Additionally, Platform Express supplies an environment in which designers can design and verify memories and peripherals from commercial intellectual property providers.
"Memory bandwidth has become a significant bottleneck for high-performance SoC designs," says Sanjay Srivastava, CEO and president of Denali Software. "Platform Express gives designers the ability to address these types of design issues with a comprehensive platform-based methodology. Using Platform Express, designers can safely integrate our Databahn memory processor cores and quickly configure them for optimal bandwidth in the context of the surrounding SoC design."
For details, go to www.mentor.com.
