IC-Design Analyzer Checks Clock-Domain Crossings; Creates Constraints

Feb. 25, 2011

An increasingly critical area of chip design is that of clock-domain crossings (CDCs), and more than ever CDCs are plaguing FPGA designers. Blue Pearl Software's tools now are friendlier than ever to FPGA designers, running natively under Windows and Linux.

David Maliniak

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Blue Pearl Software

An increasingly critical area of chip design is that of clock-domain crossings (CDCs). This goes not only for ASICs and systems-on-a-chip (SoCs), but also for FPGAs as well. All the problems designers once had with multi-cycle paths in ASICs are now plaguing FPGA designers. Clock-domain crossing issues can mean power problems. They also mean a lot of time spent poring over synthesis and timing-analysis reports, looking for paths that don’t meet timing, and then going back to the functional level to determine how to constrain the design so that it does meet timing requirements.

In the latest iteration of its software, Blue Pearl Software has emphasized ease of use, including running natively under both Linux and Windows. The idea is to make the Blue Pearl Software Suite available to a broader design community, and especially the “average” FPGA designer. Moreover, because designers are wont to distrust tools that tell them they’ve found complex faults in multicycle paths, Blue Pearl has endowed the tool to visually display the results of its work.

This is embodied in what Blue Pearl terms its Visual Verification Environment, which enables users to obtain quick feedback on design structure and hierarchy. It automates design analysis and CDC checking and allows users to perform a differential analysis on different design revisions. From that analysis, users can easily view generated SDC timing constraints, SDC assertions, and timing exception paths.

Upon analyzing the design, the tool generates design constraints in .sdc format (see the figure). The visual environment shows the relevant path, highlighting it in the schematic. In this view, the designer can immediately verify whether the path is false or not, and whether the generated constraint is correct. The alternative is to manually trace from the timing-analysis report at the netlist level to the functional level to determine which paths are critical for timing.

The Blue Pearl Software Suite, including modules for design analysis, SDC generation, and validation with the Visual Verification Environment, is available now. Pricing per module starts at $20,000.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.