Multicore Micro Features Adaptive Dynamic Voltage Control
What you’ll learn:
- Why ultra-low-power micros are a challenge to design.
- How power management works in NXP’s MXC L family.
Applications that rely on battery power or energy harvesting typically need to be designed using power-efficient microcontrollers. NXP’s MXC L family targets this space. Its dual-core design provides developers with flexibility and its ultra-low-power operation suits it for a wide range of applications.
I talked with Jeff Steinheider, General Manager of Industrial Edge Processing at NXP, about this new microcontroller family (watch the video above). It includes a demo showing the MXC L in action.
Microcontrollers Have Low-Power Design Challenges
Low-power microcontroller design and operation is addressed in numerous ways. Choosing efficient silicon implementations is one methodology, as evidenced by Ambiq’s subthreshold optimized technology (SPOT). Developers can also take advantage of multiple power modes, or approach power control of the processor and peripherals in a fine-grain fashion.
NXP’s MXC L applies these methods along with a technology called Adaptive Dynamic Voltage Control (ADVC). ADVC is built into the MCX L.
According to Eli Hughes, “The device core voltage, typically 0.9 V for a 40-nm ULP process, is dynamically tuned by the AVDC. The ADVC will adjust the system operation point to ensure the core supply Vop is running as close as possible to the internal transistor threshold voltage Vt. Power consumption scales with the operating voltage as ∆Vop2.”
The idea behind ADVC is to reduce the core operating voltage as much as possible. Hughes noted that a change from 0.9 V to 0.65 V will result in cutting overall power requirements by half. ADVC takes into account environmental conditions such as temperature.
Presenting the MCX L Architecture
The MXC L looks a lot like most multicore microcontrollers (Fig. 1). The main processor core is a 96-MHz Arm Cortex-M33 with floating-point, SIMD, and DSP instruction support. There’s also a Cortex-M0+ that runs at 10 MHz. The latter can run by itself using less power than the main core.
The processor cores share access to 512 kB of flash memory and 128 kB of SRAM. And a 32-kB ROM includes secure-boot support, which is an additional 32 kB of low-power SRAM. NXP’s chips employ EdgeLock security and the MCX L can incorporate EdgeLock PKC accelerators to enhance public key encryption that includes support for SHA, AES and PKC. Tamper and intrusion detection are also part of the security mix, as is lifecycle-management support.
The low-power peripheral mix including a 16-bit analog-to-digital converter (ADC) that runs at 2 or 3.15 MSPS in 12-bit mode. An additional 12-bit ADC is available on some parts. A 4- × 52-segment LCD drive and 8×8 keypad input sensor are also optional.
The peripherals split into real-time and ultra-low-power (ULP) always-on (AON) domains. The latter are designed to significantly reduce the system’s operating power requirements with the processing cores shut down.
Getting Started with the MCX L
A number of NXP Freedom boards are available with an MCX L microcontroller on-board (Fig. 2). The Freedom boards incorporate Arduino and mikroBUS headers. NXP’s Expansion Board Hub website lists a variety of plug-in peripheral boards.
The MCUXpresso is an Eclipse-based integrated development environment (IDE). The chip family works with a range of RTOSes, including FreeRTOS and Zephyr.
