Master The Fundamentals Of Your Gallium-Nitride Power Transistors

April 29, 2010
Breakthroughs by EPC in processing gallium nitride (GaN) have produced enhancement-mode devices with high conductivity and hyper-fast switching

GaN power transistor structure
On resistance of GaN and silicon
Transfer characteristics curve
Curves for the EPC1001
Figures of merit
EPC1010 transistor

The basic design requirements for power semiconductors are efficiency, reliability, controllability, and cost-effectiveness. High-frequency capability adds further value in system size and transient response in regulators and fidelity in class D amplifiers. Without efficiency and reliability, a new device structure would have no chance of economic viability.

Many new structures and materials have been considered. Also, recent breakthroughs by EPC in processing gallium nitride (GaN) have produced enhancement-mode devices with high conductivity and hyper-fast switching, with a silicon-like cost structure and fundamental operating mechanism.


A device’s cost effectiveness starts by leveraging existing production infrastructure. EPC’s process begins with inexpensive silicon wafers. A thin layer of aluminum nitride (AlN) is grown on the silicon to isolate the device structure from the substrate. The isolation layer for 200 V and below devices is 300 V. On top of this, a thick layer of resistive GaN is grown. This provides a foundation on which to build the GaN transistor.

An electron-generating material is applied to the GaN. This layer creates a quantum strain field with an abundance of free electrons. Further processing forms a depletion region under the gate. To enhance the transistor, a positive voltage is applied to the gate in the same manner as turning on an n-channel, enhancement-mode power MOSFET (Fig. 1). This structure is repeated many times to form a power device. The end result is an elegant, cost-effective solution for power switching.


EPC’s GaN transistors behave very similarly to silicon power MOSFETs. A positive bias on the gate relative to the source causes a field effect that attracts electrons that complete a bidirectional channel between the drain and the source. Since the electrons are pooled, as opposed to being loosely trapped in a lattice, the resistance of this channel is quite low. When the bias is removed from the gate, the electrons under it are dispersed into the GaN, recreating the depletion region, enabling it to block voltage.

To obtain a higher-voltage device, the distance between the drain and gate is increased. As the resistivity of our GaN electron pool is very low, the impact on RDS(on) (on resistance) by increasing the blocking voltage capability is much lower with GaN transistors compared to silicon. Figure 2 shows the theoretical resistance times die area limits of GaN and silicon versus voltage. EPC’s first generation of devices is shown as well.

After 30 years of silicon MOSFET development, silicon is near its theoretical limit and progress has slowed to where small gains require significant development resources. GaN is young in its life cycle and will see significant improvement in the years to come.


The threshold of GaN transistors is lower than that of silicon MOSFETs. This is possible because of the almost flat relationship between threshold and temperature along with the very low gate-to-drain capacitance (CGD). Figure 3 shows the transfer characteristics curve for the EPC1001, 100-V, 5.6-mΩ transistor. The negative relationship between current and temperature provides good sharing in the linear region. Because the device starts to conduct significant current at 1.6 V, a low impedance path is required from gate to source when the device needs to be held off during dV/dt.


RDS(on) versus gate-to-source voltage (VGS) curves are similar to MOSFETs. EPC’s first-generation GaN transistors are designed to operate with 5-V drive. Figure 4 shows the set of curves for the EPC1001. The curve shows that RDS(on) continues to decrease as the absolute maximum gate voltage is approached.

As there is negligible gate drive loss penalty, GaN transistors should be driven with 5 V. The temperature coefficient of RDS(on) of the GaN transistor is positive. The magnitude is significantly less than MOSFETs. The 125°C point is 1.45 times the 25°C point for the EPC1001, compared to 1.7 for silicon. This advantage increases with increasing voltage.


The lateral structure of the GaN transistor makes it a very low-charge device as well. It can switch hundreds of volts in nanoseconds, giving it multiple-megahertz capability. This will lead to smaller power converters and higher-fidelity class D amplifiers. Most important in switching is CGD. The EPC GaN FET’s extremely low CGD leads to very rapid voltage switching. Gate-to-source capacitance (CGS) is large compared to CGD, giving GaN transistors excellent dV/dt immunity.

CGS is small when compared with silicon MOSFETs, giving them very short delay times as well as excellent controllability in low-duty-cycle applications. A 48- to 1-V buck regulator has been demonstrated at 1 MHz using 100-V GaN transistors from EPC. Drain-to-source capacitance (CDS) is also small versus silicon. Capacitance curves for GaN are similar to those for silicon except that with a similar resistance, its capacitance is significantly lower.


Series gate resistance (RG) limits how quickly the capacitance of a FET can be charged or discharged. Silicon MOSFETs are limited to using polysilicon or silicide where GaN transistors use metal gates. The metal gates enable GaN to have gate resistances of a couple tenths of an ohm. This low gate resistance also helps with dV/dt immunity. For isolating the gate, oxide growth is not an option with GaN. The gate leakage current of GaN transistors is higher than that of silicon MOSFETs. Gate leakage on the order of 1 mA should be expected.


Total gate charge (QG) is the integral of CGS plus CGD over voltage. A common figure of merit that accounts for both on-state and switching performance is (RDS(on) x QG). Figure 5 offers figures of merit for GaN transistors versus best-in-class silicon MOSFETs for 100-V devices. The RxQ figure of merit advantage increases as voltage increases.


As seen from Figure 1, EPC’s GaN transistor structure is a purely lateral device, absent the parasitic bipolar junction common to silicon MOSFETs. As such, reverse bias or “diode” operation has a different mechanism but similar function. With zero bias gate to source, there is an absence of electrons under the gate region. As current is forced from source to drain, drain voltage decreases. A positive bias on the gate is created relative to the drift region, injecting electrons under the gate.

Once the gate threshold is reached, there will be sufficient electrons to form a conductive channel. The benefit to this mechanism is that no minority carriers are involved in conduction, and therefore no reverse recovery losses. While reverse recovery charge (QRR) is zero, output capacitance (COSS) has to be charged and discharged with every switching cycle.

For devices of similar RDS(on), GaN transistors have significantly lower COSS than silicon MOSFETs. As it takes threshold voltage to turn on the GaN transistor in the reverse direction, the forward voltage of the “diode” is higher than the silicon transistor. Therefore, care should be taken to minimize diode conduction.


EPC’s GaN transistors are insulated from the substrate. This allows monolithic fabrication of multiple transistors in any configuration in addition to efficient, common heatsinking without the need for an insulating interface. It also forces the current for both drain and source to be collected on one side of the die.

To keep the resistance low in the metal layers that collect the current, these paths must be kept short. To accomplish this, wafer level line grid arrays are used where drain and source lines are alternated. Standard line pitches are 0.4 mm and 0.6 mm. Figure 6 shows the EPC1010, a 200-V, 25-mΩ transistor. Underfill can be used where this does not allow compliance with safety agency creepage distance requirements.


EPC brings the enhancement mode to GaN. This allows immediate realization of the disruptive gains in efficient high-frequency and low-duty-cycle power conversion. Other “exotic” technologies are either cost-prohibitive or use depletion mode. Depletion-mode devices lose control when there is no power. They also require new development in control ICs.

GaN transistors will yield a leap in class D audio technology by enabling efficient switching at frequencies above the AM band. Fidelity will approach class A and class AB systems without all of the size and weight limitations of linear amplifiers.

In information processing and storage systems, the whole power architecture can be reevaluated to take advantage of the switching capabilities. As output voltage increases for ac-dc converters, efficiency goes up. As bus voltage increases, transmission efficiency goes up. As frequency increases, size goes down.

EPC GaN enables the last stage, which permits the first two while increasing ac-dc efficiency when used as their synchronous rectifiers. They also allow for intermediate-stage converters to be removed for single-step conversion, saving the size and cost of the intermediate stage converter.

Sponsored Recommendations


To join the conversation, and become an exclusive member of Electronic Design, create an account today!