Optimizing Solid State Drive Power Architecture

April 26, 2012
Solid-state drive system designers need to carefully consider their design objectives when specifying the power supply. Considerations of EMI, size, and efficiency dictate three different, optimized SSD power supply solutions with tradeoffs in these and other areas. By considering the design goals, the optimal switch-mode power supply allows the solid-state drive to achieve its highest performance and fulfill the needs of many applications.

Solid-state drive (SSD) designers have many competing requirements when it comes to powering their drives. First, there is the size of the power supply, which must not increase the form factor of the SSD, since the SSD usually must be form-factor compatible with the hard disk drive (HDD) it is replacing. Second, there are ever-increasing efficiency requirements for the whole system in both standby mode, when nothing is being read from or written to the SSD, and in maximum power mode, when reading and writing at maximum capacity. These efficiency targets often drive specific SSD certifications, such as Energy Star, which are critical for marketplace acceptance. A final concern is how the power supply responds to the changing needs of the end user. Can it respond fast enough to supply a large amount of power to the SSD when it turns fully on after being idle? Or does the SSD “hang” if the host accesses it too quickly or too extensively all at once?

SSD Architecture

Fig. 1 shows a typical drawing of the SSD system in a server. A 12-V bus powers a switch mode power supply (SMPS) that provides 3.3V to the SSD. NAND flash is used for the memory due to low cost and its ability to retain data without power. An ASIC or other processor communicates with the host and manages the data flow. 2.5V and 1.8V are shown for the typical needs of the ASIC.

The SMPS must be a synchronous buck converter, versus a linear regulator or asynchronous buck converter, to provide high efficiency at such high load currents. It also must have a power-save mode to keep the efficiency above a minimum value even when the SSD idles. Third, it must operate from a medium voltage, 12-V input bus and provide output voltages down to 1.8V and lower, depending on the needs of the ASIC. Finally, the SMPS should optimize its size, efficiency, and response time to the needs of the SSD system.

For SSDs to begin gaining market acceptance, they were required to be backwards-compatible in their form, fit, and function with HDDs. When a user’s HDD failed, sometimes after less than a year of operation, SSDs became a higher reliability replacement. The user simply ordered a SSD in the same form factor as the failed HDD and the reliability of the computer or server received an instant upgrade.

With the continually falling price of SSDs, they are no longer simply replacements for HDDs that have reached their end of life. Now, SSDs are being designed into high reliability sectors, such as enterprise servers, and consumer applications like notebooks. Small size is important for these applications, though the form factor of the SSD no longer has to exactly match that of a HDD.

In either case, the ability to achieve a sufficiently small solution size is a strong selling point for the SSD. Although not the largest subsystem in the SSD, the power supply occupies significant board space since the SSD circuitry is powered by several individual SMPSs. The typically tall inductors required even stretch the limits in the z-direction —making size a three-dimensional concern.

Efficiency

An important overhead cost for servers is their power consumption. This consists of both the power consumed by the drives as well as the energy required to remove the generated heat from the surrounding air to keep the server’s room cool. With the increasing price of energy and an emphasis on having “green” operations, energy efficiency is a driving requirement for SSDs more than ever.

In the notebook world, a more efficient SSD allows longer battery run time as well as lower case temperature. Both are highly desirable selling features that the end user understands and is willing to pay for. Especially for notebooks, the power consumption and efficiency of the SSD when idling is critical as this parameter greatly affects the battery run time. Compared to HDD systems, SSD batteries last longer, notebooks run cooler, and hard drives do not fail as often.

Even if the idling power consumption is low and efficiency high, what happens when the server or notebook wakes up and reads from and writes to the SSD? Does the power supply have the capability to transition from this idling state to the full power state fast enough to avoid a reset of the SSD, due to loss of supply voltage?

This is a very tough design challenge for SMPS designers. On the one hand, the SMPS should be nearly off, with as few circuits running as possible, such that its power consumption is the lowest when in idle mode. On the other hand, the SMPS’s circuitry should be biased up and ready to quickly respond to the imminent access of the SSD by the user. These competing directives require a careful balancing act and tradeoffs examination. An IC that is specifically designed for the requirements of SSDs provides the optimal solution.

Focusing on the SMPS that powers the NAND flash with 3.3V, while keeping in mind the other power needs on the SSD, three possible power solutions for various SSDs are analyzed: a full-featured solution, the smallest solution, and a solution tailored for high efficiency. An example load current step of 10 mA to 1 A is used for assessing the response time of each solution, as it is typical of a SSD being accessed after being idle.

One type of SSD application requires very tight electromagnetic interference (EMI) controls and low radiated emissions. This might be for use in a hospital or airplane setting where numerous devices are transmitting data in the air and emitting EMI at various frequencies. For such applications, the SSD should have tight control over its switching frequency to keep any emissions in a narrow band where they are easily controlled, reduced, or filtered out. This power solution is considered full-featured since it contains a complicated feature that is unnecessary in the majority of SSD applications. Such a full-featured solution is the TPS62110, which provides the efficiency characteristic shown in Fig. 2 and response time shown in Fig. 3. This full-featured solution yields a solution size of about 175 mm2, but due to the relatively large inductor required, has a maximum component height of 3.2 mm.

A second type of SSD application requires the smallest possible total solution size. This might be for a high performance notebook or simply to match the form factor of a particular HDD. To achieve small size, a SSD-optimized power solution is needed — one that increases the switching frequency to make the output filter smaller and reduces the features to the minimum required. The TPS62140 fulfills both of these goals and supports a solution size of only 74 mm with a maximum height of 2 mm. Fig. 4 and Fig. 5 show its efficiency and response time.

A third type of SSD power solution requires the highest efficiency over the entire load range. This is of extreme importance in a server environment where cooling and electricity costs are huge overhead concerns while a slightly larger solution size is tolerable. Fortunately, the smallest power solution contains a feature that selects the device’s switching frequency for either smallest solution size or highest efficiency. If operated with highest switching frequency, as done in the second example, the solution size is an absolute minimum. However, the switching lo sible. This translates into the maximum amount of area for other components of the SSD system, including possibly a SSD with more gigabytes of storage. If a slightly larger SMPS solution can be accommodated, the highest efficiency solution mostly exceeds the efficiency of the full-featured solution while occupying only half the area. Its efficiency at higher load currents is not limited by the SMPS itself, but by the inductor chosen. At higher loads, the resistive losses (inductor DCR and MOSFET RDS(ON)) dominate over the frequency dependant losses. Thus, the efficiency advantage of operating with the reduced switching frequency diminishes as the load increases. With a physically larger inductor with lower DCR, the highest efficiency solutionís efficiency exceeds the efficiency of the full-featured solution across the entire load range. As currently implemented in example 3, its efficiency at heavy loads is comparable to the full-featured solution but using half the solution size and height.

A final challenge confronting SSD designers is designing the power supply for each of their different capacity SSDs, which require varying amounts of current depending on capacity. If a certain SSD only needs 500 mA of current, then the power supply used on a 3 A SSD is over designed and costs more than needed. A scalable power supply is needed for different capacity SSDs that allows design reuse and reduces NRE costs associated with brand new SMPS designs. Fortunately, the SMPS IC used in the smallest solution and highest efficiency solution is pin-compatible with higher and lower load current versions. When lower capacity SSDs are designed, the lower current SMPS IC can be dropped in place, thus reducing the bill of materials (BOM) cost.

Fig. 6
Fig. 7
Fig. 8
Table 1

References

  1. TPS62110 datasheet
  2. TPS62140 datasheet
  3. TPS62130 datasheet
  4. TPS62150 datasheet

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About the Author

Chris Glaser | Applications Engineer

Christopher James Glaser is an applications engineer for TI’s Low Power DC/DC group. In this role, he supports customers, designs evaluation modules (EVMs), writes application notes, trains field engineers and customers, and generates technical collateral to make TI parts easier to use. He received his BSEE from Texas A&M, College Station, Texas. He can be reached at [email protected].

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