IGBTs For Three-Level Inverters Can Meet Energy-Efficient Design Needs

July 1, 2009
With limited availability of electrical energy and increasing oil prices, there is a trend to reduce electrical energy consumption and promote research into alternative sources of energy. One answer is multilevel inverter technology.

When we speak of efficiency, we are referring mainly to electrical efficiency. This usage, however, is a restriction of the meaning of the word efficiency itself. In power-electronics applications the main goal pursued by engineers in the development of a new product is to maximize different types of efficiency — such as electrical and thermal efficiency — as well as to optimize harmonic distortion and overall dimensions.

The above-mentioned goals must be fulfilled in line with other increasingly tighter goals: the achievement of economic efficiency and shortened development times. One question that arises in this context is whether more powerful modules with better efficiency rates can meet the all-important efficiency goals.

SEMITOP® power modules boast excellent thermal performance, integrating the latest silicon technologies and highly innovative circuit topologies to provide maximum efficiency and cost effectiveness. The SEMITOP product range has been expanded, adding a new module specifically developed for three-level inverter applications. Three-level inverter topology is being used increasingly in UPS applications, including those with medium-low power ratings (5 to 40 kVA).

The SEMITOP isolated power modules are for PCB soldering. The use of a single mounting screw and a copper-baseplate-free design ensure excellent thermal performance and unbeatable reliability in application. Reliability is also validated in an extensive qualification program based on 17 different tests performed for more than 10,000 hours.


Multilevel inverter technology is based on a rather simple concept: IGBT modules are connected in series, allowing for voltage ratings far higher than the IGBT reverse-blocking voltages. This concept was first introduced for high-voltage and high-power converter applications to enable the use of standard IGBTs in applications with voltage ratings ranging in the tens of thousands.

The use of multilevel inverters is a simple way of improving efficiency in dc-ac conversion. The converter produces an output waveform very close to a sinusoidal wave, with extremely low harmonic distortion levels. This boasts two advantages. The switching frequency can be lower than that of a typical two-level application, allowing for reduced silicon losses; and a reduced output filter results in a reduction in overall dimensions and costs.

A typical three-phase inverter designed in half-bridge topology, as shown in Fig. 1 (left) allows for an output-voltage waveform that can switch only between two voltage levels. The topology in Fig. 1 (right), by contrast, allows for an output-voltage waveform that switches through three voltage levels, which is why this topology is also known as three-level inverter topology.


We will now analyse the principle behind a three-level inverter to ascertain the differences between it and a conventional two-level inverter [1]. For a three-phase three-level inverter, a structure similar to that used with 12 electronic devices (IGBT) is needed (Fig. 2). Each phase will switch across three voltage levels (+V dc/2, 0, and -Vdc/2). In a structure such as this the maximum voltage across the IGBT is limited to half the maximum dc link voltage (Vdc/2). This occurs because the IGBTs are connected to the neutral point (MP) by two fast diodes called neutral clamp diodes.

Three-phase two-level-inverter (PWM)-generation algorithms [2] can also be applied to multilevel inverters. The algorithms with a triangular carrier waveform produce the best benefits in terms of harmonic distortion reduction, i.e. a three-level inverter needs both a carrier and a reference. In this case the number of triangular carriers is equal to L-1, where L is the number of voltage levels. For a three-phase three-level inverter this means that two triangular carriers and one sinusoidal reference are needed.

Three alternative PWM strategies with differing phase relationships can be used for a three-level inverter:

  • Alternative phase-opposition disposition (APOD), where carriers in adjacent bands are phase-shifted by 180°.


    Phase-opposition disposition (POD), where the carriers above the reference zero point are 180° out of phase with those below zero.

  • Phase disposition (PD), where all carriers are in phase across all bands.

PD strategy is used most frequently because it produces minimum harmonic distortion for the line-to-line output voltage. Triangular carriers and sinusoidal reference profiles, as well as IGBT and NCD current profiles, are shown in Fig. 4.

A three-level inverter appears to comprise highly complex circuitry compared with a two-level inverter. The resulting technical and economic advantages, however, are the reasons why the use of three-level inverters is strongly recommended.

In Table 1, two standard modules will be compared in the same application with identical boundary conditions ( [3],[4]). The IGBT and diode conducting and switching losses are calculated using the formulae given in Table 2 [5], [6].

A three-level inverter features an IGBT with a lower reverse-blocking voltage: 600 V instead of 1,200 V. The 600-V chips are normally faster and thinner than 1,200-V chips. The silicon in a three-level inverter therefore has lower switching losses and a lower forward-voltage drop. As shown in Table 3, the total losses per single arm of the three-level inverter are 60% lower than those of the two-level inverter. Q2 and Q3 switching losses are negligible. D1 and D4 diodes carry a very low current value since the current of Q1 commutes to D5; the current of Q4 commutes to D6, and the current of Q2 commutes to Q3. Clamp diodes carry the full load current.

Fig. 3 shows the overall losses as a function of the switching frequency for a single inverter leg (3L vs. 2L). In order to reduce noise pollution, UPS applications in the 20-kVA range work with switching frequencies above the audible human hearing range. In this switching frequency range, the total leg losses for a 3L inverter are significantly lower than those of a 2L inverter.


Moreover, in a 3L inverter, the output-voltage waveform is very similar to a sinusoidal wave, which is why the 3L inverter needs very small output filters. Stresses acting on the 3L IGBTs and diodes are therefore reduced, thus increasing the long-term reliability and the overall application efficiency. From an economic perspective, in this specific analysis a 3L inverter leg based on 600-V silicon is 25% cheaper than a 2L inverter leg with 1,200-V silicon.


The real benefit of a 3L inverter is the reduced stress on the power switches, owing to the lower losses as well as the fact that the output voltage switches through three voltage levels. The resultant output-voltage waveform is almost sinusoidal with a reduced harmonic distortion, leading to the use of smaller output filters. Reduced overall losses also mean that a smaller heat sink can be used. A smaller heat sink and smaller output filter allow for reduced overall dimensions in UPS applications, which in turn reduce the overall application costs.


For the aforementioned reasons, the use of a standard SEMITOP® module in 3L inverters for UPS applications can maximize electrical and thermal efficiency, reduce the time to market and, more importantly, reduce the overall costs for the UPS application.



    Grahame Holmes, Lipo - “Pulse width modulation for power converters: principle and practice”. Pages 42-49

  2. Grahame Holmes, Lipo - “Pulse width modulation for power converters: principle and practice”. Pages 467-469

  3. SK60GB128 datasheet. http://www.semikron.com/internet/ds.jsp?file=2469.html (referenced 13.02.2007)

  4. SK30MLI066 datasheet. http://www.semikron.com/internet/ds.jsp?file=2782.html (referenced 17.01.2008)

  5. Gjermund Tomta, Roy Nielsen. “Analytical Equations for Three Level NPC Converters”, 9th European Conference on Power Electronics and Applications, EPE 2001. Graz, August 27 to 29, 7 pages.

  6. Semikron application manual. Web-document. http://www.semikron.com/internet/index.jsp?sekId=13 (referenced 14.9.2005)

  • DCB in direct contact with heat sink: no baseplate needed

  • A ceramic layer for insulation

  • Pins for PCB soldering

  • One mounting screw for easy mounting

  • Current rating

    • Up to 200A for 600-V IGBT
    • Up to 100A for 1,200-V IGBT
    • Up to 300A for MOSFET
  • Reduced assembly costs

  • Optimum thermal resistance

    • Up to -30% compared with isolated TO
    • Up to -18% compared with IMS
  • Combines a wide range of topologies and chip technologies: input bridges, inverters, AC switches, half-bridges, converter-inverter-brake, brake chopper
  • Compact design with cost and space savings
  • Uses pins with extremely low series resistance: up to 14% lower conducting losses than competitor technology
  • All modules are RoHS compliant

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