High-Speed ATE – The Future of High-Speed ATE

Nanometer SOC device manufacturing requires flexible at-speed functional testing.

The semiconductor industry gradually is transitioning to nanometer manufacturing processes. With this technology comes one big benefit: An increased transistor count is almost free. On the other hand, CMOS processing has changed dramatically, and as a result, nanometer SOCs exhibit new types of fabrication defects.

One example is an increased number of timing failures that show up particularly at high frequencies. Other examples include crosstalk, clock skew and synchronization issues, and parametric failures of high-speed I/Os that, due to their analog nature, are especially sensitive to injected noise from adjacent digital cores.

To manage the associated quality and cost-of-test challenges, new design-for-test (DFT) techniques and alternative test methods are being explored. In particular, AC scan and built-in self-test (BIST)/loopback techniques are increasingly being used to improve fault coverage on timing-related failures for the high-speed portions of the devices.

Questions naturally arise: Will these enhanced structural testing developments eventually overcome the need for high-speed ATE at gigahertz data rates? Or, will at-speed functional and parametric testing on high-speed ATE systems continue to be technically required and economically justified in the future?

Nanometer Fabrication Defects and Their Consequences
One example of altered defect characteristics is the massive increase in timing-related faults.1 These often result in failures only at high frequencies rather than at DC, such as stuck-at faults. In contrast to DC failures, timing-related issues only can be detected via at-speed tests.

With decreased device dimensions comes increasing statistical variability of key transistor parameters such as gate oxide thickness, threshold voltage, effective transistor length, and leakage current. These all affect timing.

The root causes for this variability range from nonideal scaling of device parasitics to imperfect lithographic printing. As an example, the significantly reduced number of injected dopant atoms in nanometer-geometry devices increases the effect of random dopant fluctuations. As shown in Figure 1, these kinds of factors cause large variations in a chip's speed and consumed power.

Figure 1. Impact of Parameter Fluctuations on Speed and Consumed Power for a Large Sample of Chips2

Further aggravating the high-speed performance of small-scale devices are increased capacitive crosstalk effects and RC interconnect delays. Eventually, propagation delays caused by the interconnects dominate transistor gate delays. This effect contributes to more performance outliers and the need for speed binning in production testing.

For such complex nanometer devices, traditional at-speed functional testing addresses signal integrity issues such as IR drop, inductive crosstalk, substrate coupling, and electromigration, which cannot be revealed by current simulation techniques. At-speed testing also achieves the required timing closure.

Low yields often are an issue during the production ramp of new nanometer designs, especially because defects seem to have a stronger dependence on the application than in previous technologies. More comprehensive tests are needed to achieve the required quality level for production devices. In conjunction with DFT capabilities, at-speed functional testing provides the essential feedback loop for understanding the failure mechanisms inherent in new fabrication processes.

Synchronization Challenges in SOC Designs System-wide clock synchronization is one of the main challenges for large nanometer designs. While minimum clock periods of high-speed designs have decreased, die sizes remain large because more and more components are integrated onto the same die. As a result, the associated clock skew, which is roughly proportional to the interconnect delay, can be a significant portion of the clock period, and across-chip communications in synchronous designs can require more than one clock cycle.

Sophisticated clock deskewing techniques are used to address these challenges. In very large designs, new approaches such as globally asynchronous, locally synchronous (GALS) architectures are replacing conventional clocking schemes. Nevertheless, the data transfers between different domains within an SOC design still must be resynchronized. At-speed functional testing can unravel these kinds of synchronization issues, but other at-speed methodologies such as AC scan cannot.

Challenges of Testing High-Speed I/Os
Today's high-performance SOC designs incorporate a large variety of high-speed I/O buses and protocols. A wide mix of different signalling types can be found, from simultaneous bidirectional to unidirectional signalling and single-ended to low-voltage differential. The traditional wide, parallel, source-synchronous bus architecture with a separate clock signal increasingly is being replaced by narrow, serial, embedded-clock technologies. Serializer/deserializer (SerDes) cells are used, which have a clock and a data recovery (CDR) unit in the device receiver ports to extract the clock signal from the incoming data stream.

PC chipset devices exemplify mixed I/O types (Figure 2). PCI Express and S-ATA, for example, both use embedded clock technologies with unidirectional, low-swing differential signalling. While PCI Express may comprise up to 32 lanes running at a data rate of 2.5 Gb/s, S-ATA only supports one lane at 1.5 Gb/s or 3 Gb/s.

Figure 2. Example of a Recent Intel-Based PC Chipset Architecture With a Memory Bridge (Northbridge) and an I/O Bridge (Southbridge)

In contrast, DDR memory interfaces and Intel's front-side bus (FSB) architecture currently use single-ended, bidirectional, source-synchronous techniques. The current FSB data rate of 800 Mb/s is expected to increase soon to 1,066 Mb/s and might even reach 1.6 Gb/s.

To cope with such hardware variations as well as uncertain market timing, flexible test equipment is required. Hundreds of high-speed pins are needed, but multiple clock domains also operate at odd speed ratios because different interfaces must be tested concurrently.

The massive integration of SerDes macro cells into consumer SOC devices raises complex test challenges associated with such I/Os, for example, extensive parametric testing with the emphasis on jitter. These tests seem to be even more important for highly integrated SOC devices, because their numerous cores may negatively impact the actual off-chip data transmission. Some tests may need to be done in a production environment.

For parametric testing, highly integrated digital ATE channels are more appropriate than traditional rack-and-stack or mixed-signal instrumentation. An input analog bandwidth of several gigahertz, low intrinsic system jitter, and very high timing accuracy are required. Because it addresses all these test challenges, at-speed functional test will remain the primary tool for verification of a chip's correct logical and electrical performance. These are the two main tasks undertaken during the debug and characterization phase of high-speed devices.

The Coexistence of At-Speed Functional Testing and At-Speed DFT
As efforts to reduce the cost of test continue, the broad development and application of on-die testability resources are constantly pushed further. For the identification of timing-related issues, at-speed structural tests for transition-fault, and path-delay testing of critical paths as well as BIST/loopback techniques increasingly are used.

One example of a structural at-speed methodology is AC scan,3 and indeed, the support for AC scan in EDA tools constantly improves. However, the switching activity during AC scan testing can be completely different from functional testing and, for this reason, may not mimic real application conditions. As a consequence, such approaches require extensive correlation to actual functional testing.

Even with good correlation, there are other potential problems that can lead to increased yield losses or test escapes. An increased yield loss, for example, happens if delay faults show up on paths that do not contribute in the real application.

Imprecise delay tests can be another source of yield loss as well as test escapes. Delay-path measurement errors of only tens of picoseconds can represent 5% of the internal clock periods. To date, there is no known way of adding margin testing to delay-path measurements, so these errors can result in yield loss or test escapes.

Combining on-chip BIST structures with serial loopback schemes is another popular technique for at-speed production testing, in particular for SerDes I/O cells. With the use of special ATE loopback cards, such as the Agilent 93000 BIST Assist 6.4, test coverage can be enhanced beyond basic functional testing by supporting parametric measurements as well (Figure 3).

Although DFT or other low-cost techniques may be the most economic test solutions for high-speed devices featuring many high-frequency I/Os, there still is a strong desire for ATE to provide at-speed stimulus and captures, especially before a product becomes mature. When DFT fully replaces at-speed functional testing, the achievable fault coverage tends to be compromised. This can be a potential risk, especially for new I/O technologies that often push process technology to its limits.

In addition, DFT still is a maturing technology, and different silicon vendors follow different DFT deployment strategies. For this reason, at-speed DFT is not consistently implemented across the industry. Even in production, the entire industry will not likely fully replace at-speed functional testing with at-speed DFT in the foreseeable future.

Key Requirements for High-Speed ATE Channels
Especially for design characterization, ATE high-speed drive and capture capabilities must be paired with high timing accuracy. To some extent, this holds true even for production testing because any additional guard-banding required to account for tester inaccuracies leads to additional manufacturing yield losses. Equally important, the ATE functionality must be provided cost effectively because semiconductor vendors face tremendous cost pressures.

The requirements for high-speed ATE can be summarized as follows:

High Flexibility: the capability to cover a wide variety of different I/O types. Full Scalability: the capability to cover the complete range of required speeds and needed pin resources. Data rates range from hundreds of megahertz to several gigahertz, and the required pin-count can be as high as 2,000 pins. High Performance: high accuracy and fast throughput.

Support of multiple clock domains.

  • Affordable cost.

  • Conclusion
    Despite recent advances, it is unlikely that at-speed structural and BIST-based loopback testing can solve all issues with timing-related nanometer fabrication defects. This is especially true as life cycles for most products become shorter and shorter and it becomes more difficult to verify and optimize DFT circuitry to the necessary level.

    In many cases, DFT-based techniques will coexist with a limited number of functional at-speed patterns which fill in missing test coverage of DFT-only approaches. As a result, affordable high-speed, high-density, and highly versatile ATE will remain key to successful semiconductor manufacturing.

    The author greatly acknowledges the assistance of Bernd Laquai and Christof Baschang of Agilent Technologies.

    At-Speed I/O Solution

    The Agilent 93000 SOC Series has added the Pin Scale 3600 Pin Electronics Card to support high pin-count devices and multisite configurations with up to 2,048 pins. Built on the Test Processor-Per-Pin architecture of the 93000, the card provides up to eight independent clock domains satisfying complex timing needs for concurrent at-speed testing of multiple buses running at nonfriendly speed ratios.

    Each test pin can be configured from 800 Mb/s to 3.6 Gb/s. Because each pin offers both single-ended and differential I/O test capability, a wide range of interfaces can be tested, including DDR, G-DDR, PCI Express, S-ATA, HyperTransport, and Front-Side Bus. Each pin can be software configured for speed, memory, and I/O type, enabling the ATE to be matched to the device.

    The architecture eliminates the intrinsic jitter associated with the traditional change-period-on-the-fly concept. This results in a low differential clock jitter of less than 4-ps rms or a differential pin-edge placement accuracy of better than  30 ps.

    1. Aldrich, G., and Cory, B.,  Improving Test Quality and Reducing Escapes,•  Proceedings of the Fabless Forum, Fabless Semiconductor Association, 2003, pp. 34-35.
    2. Gelsinger, P.,  GigaScale Integration for Teraops Performance Challenges, Opportunities, and New Frontiers,• Keynote Address at the Design Automation Conference, 2004.
    3. Lin, X. et al.,  High-Frequency, At-Speed Scan Testing,• IEEE Design and Test of Computers, September-October 2003.

    About the Author
    Clemens Leichtle is a senior test application consultant in the Computation and Communication Semiconductor Test Division of the Agilent Technologies Automated Test Group. Before joining Agilent in 2000, Dr. Leichtle was with Siemens Semiconductors/Infineon Technologies as an R&D engineer focusing on the development of EDA layout extraction and circuit resimulation design flows optimized for memory products. He holds a Ph.D. in physics from the University of Ulm, Germany. Agilent Technologies, e-mail: [email protected]


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