DesignCon to address 2.5-D and 3-D devices

Our February 2012 features are online, and they include my article on 2.5-D and 3-D devices. DesignCon, convening in Silicon Valley next week, will also address the topic.

One session, sponsored by Apache Design, is titled “CPS for 3D-IC and Power-Thermal-Mechanical-Electrical Applications.” It will include speakers from Micron, LSI, and Xilinx (which debuted a 2.5-D device last fall—see “Virtex-7 uses 2.5-D technology to deliver 6.8 billion transistors” in my blog archive).

The speakers will focus on the challenges created by 3-D stacked die and 2.5-D Silicon Interposer with TSV chip designs. The technologists will examine modeling and simulation challenges in 3-D-IC design and explore methodologies for power delivery, network analysis, chip-to-chip communication, and thermal integrity using real case studies. This session takes place on February 1 from 2:00 p.m. to 4:00 p.m. in Ballroom H.

For its part, Xilinx announced that Liam Madden, Xilinx corporate vice president for FPGA development and silicon technology, will discuss the benefits and drawbacks of 3-D IC standards in a panel titled “Why Do We Need 3D Design Standards?” Xilinx said its technologists will also present papers on stacked silicon interposer technology and the design benefits of using the Zynq-7000 Extensible Processing Platform (EPP).