November 7, 2012. Mentor Graphics announced at the International Test Conference its new Tessent IJTAG solution, which allows designers to reuse test, monitoring, and debugging logic embedded in existing IP blocks. Supporting the IEEE P1687 (IJTAG) standard, the solution automatically retargets test and debug commands and generates an integrated hierarchical control and data network with a single top-level interface for an entire SoC. The solution, which supports any embedded instrumentation compliant to the P1687 standard, can be used where pin count is limited or access is difficult, as in stacked die configurations. The company highlighted the new solution at the International Test Conference.
“The continued exponential growth in semiconductor device functionality and performance relies not only on continued transistor scaling as defined by Moore’s Law, but also on increased use of a rapidly expanding and functionally diverse set of reusable IP blocks,” said Steve Pateras, product marketing director at Mentor Graphics. “This trend is driving the need for test and instrument integration standards and more efficient automation solutions to maintain design schedules and costs. We are seeing increasing customer interest in adopting an IEEE P1687-based integration flow to address test and debug of the growing amount of IP in their designs.”
“The IEEE P1687 standard will play a critical role in helping debug and test teams successfully manage the growing amount of IP used in today’s complex designs,” said Jeff Rearick, senior fellow at AMD and editor of the IEEE P1687 working group. “Successful deployment of the standard will be greatly expedited by comprehensive automation support. I’m excited to see Mentor deliver this key functionality in its Tessent product line.”
The new IEEE P1687 standard creates an environment for plug-and-play integration of IP instrumentation, including control of boundary scan, built-in self-test (BIST), internal scan chains, and debug and monitoring features in IP blocks. The standard defines hardware rules related to instrumentation interfaces and connectivity between these interfaces, a language to describe these interfaces and connectivity, and a language to define operations to be applied to individual IP blocks. IJTAG replaces proprietary and incompatible IP interfaces from multiple suppliers with a standardized interface mechanism that enables plug-and-play integration of IP test and instrumentation facilities.
The Tessent IJTAG solution provides automated support for the IJTAG standard, substantially reducing the time and effort required to assemble large SoC designs from reusable IP blocks. The new product includes all the facilities needed to efficiently integrate IEEE P1687-compliant IP into a design:
- automatic verification that a given IP block is compliant to the P1687 standard,
- verification that P1687-compliant IP blocks are properly connected within a P1687-compliant access network,
- automatic creation of a P1687-compliant access network connecting IP to the top level instrument interface, and
- retargeting and merging of local IP instrumentation patterns through the P1687 network, allowing IP specific sequences to be applied from chip pins or from anywhere higher up in the system hierarchy.
“Standards like P1687 are important enablers for maximizing our design productivity,” said Tom Waayers, DFT product manager and architect at NXP Semiconductors. “After an extensive evaluation, we have determined that the new Tessent IJTAG product will enable faster integration, as well as greater scalability, as our design complexities continue to grow.”
The Tessent IJTAG product is available now in Tessent release version 2012.3.