EDA firms tout IJTAG, memory test and repair

IJTAG and memory test and repair were key topics highlighted by Mentor Graphics and Synopsys, respectively, at this year's International Test Conference. Mentor introduced its Tessent IJTAG tool, and Synopsys highlighted its DesignWare STAR Memory System 5, which supports embedded memory test, repair, and diagnostics at 20 nm and below.

Stephen Pateras, product marketing director at Mentor, noted that the new IJTAG tool facilitates the pursuit of Moore's Law and beyond, as geometries shrink below 22 nm and diversification leads to the integration of analog/RF, passive, and high-voltage/high-power devices as well as sensors, actuators, and biochips.

With such diverse devices, he said, IP reuse is the key to scalability, he said, adding htat the IEEE P1687 standard enables plug-and-play integration of embedded IP. The standard includes hardware rules for instruments and networks, an instrument connection language (ICL), and a pattern-description language (PDL). Tessent IJTAG, he said, provides comprehensive automated support for the standard, enabling automated integration of P1687-compliant IP. It can be used by IP providers to ensure compliance with the standard, by chip designers to integrate IP from various sources, by test integrators to assemble and execute tests, and by diagnosis and failure-analysis engineers to access on-chip instruments.

Pateras said that NXP partnered with Mentor to investigate P1687 and contrast Mentor's tool with NXP's in-house IP test system. Pateras said Tessent IJTAG offered significant improvements in the level of automation, reduced user-input requirements, more flexibility in test access and design, and test-data-volume reduction of up to 56%.

Robert Ruiz, senior product marketing manager at Synopsys, described the new DesignWare STAR Memory System 5 as part of the Synopsys synthesis-based test product lineup, which also includes logic test (in the form of the TetraMAX ATPG and DFTMAX compression tools), BIST for high-speed I/O IP (DesignWare IP), and yield analysis (Yield Explorer and Camelot). Sandeep Kaushik, senior product marketing manager, said that memory is dominating chips as the number of processors grows and cache size per processor grows. But as geometries shrink to 20 nm, new defects appear, resulting from overlay shift in double patterning, voltage scaling, and random dopant fluxuation.

DesignWare STAR Memory System 5, Kaushik said, is an RTL/gate-level solution for Synopsys and third-party memories that performs test, diagnostics, and redundancy analysis while supporting automatic insertion and test-bench generation. It supports standard JTAG and IEEE 1500 interfaces, tester-ready pattern generation, failure diagnostics and fault classification, and post-silicon bring-up, debug, analysis, and characterization.

The tool spans process development, IP qualification, SoC test and repair, and field reliability. Optimized algorithms can detect problems related to process variation faults, random telegraph noise, resistive opens or shorts, and address decoder delay. Compared with previous versions, the new tool provides up to 30% reduction in area needed for test circuitry, Kaushik said. In addition, the insertion of the test wrapper occurs at the memory hierarchy level, so the insertion doesn't affect the design hierarchy.

Ruiz also commented on Synopsys' approach for addressing multicore processor test costs at 2- nm. A new version of the DFTMAX compression tool cuts test costs by a factor of 2, he said, while TetraMAX diagnostics tools are tuned for 20 nm, enabling a faster understanding of yield issues. In general, he said, the Synopsys synthesis-based flow (including design RTL, synthesis, place and route, and ATPG) can save four weeks in contrast with traditional customer flows (which can require steps such as adding constraints for compression, synthesis of compression logic, stitching of compression into the design, and manual setup of ATPG).