April 2, 2013. ProPlus Design Solutions Inc., a technology provider of design-for-yield (DFY) applications, today launched NanoSpice, a high-capacity, high-performance parallel Spice simulator for gigascale circuit simulation.
In announcing NanoSpice, ProPlus unveiled a licensing model with simplified and practical control for parallelization, making it a cost-effective and powerful choice for advanced circuit simulations that designers typically don’t have.
“New simulation technology is essential for deep nanometer technology designs where process variations significantly impact circuit yield and performance,” said Dr. Zhihong Liu, ProPlus’ executive chairman, who added that designers cannot settle for capacity or performance and sacrifice accuracy. “Demand has never been greater for highly accurate, gigascale simulations for large post-layout designs.”
The need for gigascale simulations is being driven by complex designs and because of the large number of simulations required to design for variation effects. Traditional Spice simulators lack capacity requirements even with parallelization. FastSPICE simulators that deliver capacity at the cost of accuracy are losing steam as an increasing number of designs require post-layout verification that weakens circuit hierarchy. FastSPICE’s table model approach, as well as its approximated matrix solutions, is prone to unreliable results and poor usability for complicated gigascale designs with multiple operating modes and supply voltages.
NanoSpice is a pure SPICE circuit simulator matching the industry’s highest accuracy standard. Because it shares the same core Spice engine with ProPlus’ BSIMProPlus, the de facto golden device modeling software used by all leading foundries, it has built-in foundry-validated accuracy and compatibility. It has full Spice analysis features and supports industry-standard inputs and outputs.
NanoSpice runs 10 to more than 100 times faster than traditional Spice simulators. It is able to handle all circuit types, with an ability to simulate large-scale circuits of 50 million or more elements for generic circuit types, and 100 million or more elements for memory circuits.
It is suited for applications such as memory, analog/mixed-signal, I/O, custom digital, and standard-cell design. NanoSpice handles challenging designs, including the characterization of large embedded SRAM blocks, post-layout analysis of analog circuits, sign-off simulation of full-chip power IC or wireless transceiver circuits, and accurate clock tree and critical path analysis.
For example, NanoSpice was used to simulate a multi-million element, post-layout analog/digital converter (ADC) circuit in less than two days with pure Spice-comparable accuracy measured in signal-to-noise ratio (SNR). Other parallel SPICE simulators took several weeks to complete this task.
In another example, a 50 million transistor SRAM block was successfully simulated using NanoSpice in memory mode when other parallel Spice simulators could not run a design this large.
Developed to enable gigascale simulation and for handling process variations from 3-sigma to high-sigma Monte Carlo simulations with full matrix solving and without approximations in model calculations, NanoSpice uses effective model-handling and high-performance parallelization technology with high memory efficiency. In a recent evaluation, NanoSpice ran sign-off simulation on a 576 million element, full-chip memory circuit in eight hours using eight threads with 15 gigabytes of memory consumption.
NanoSpice is tightly integrated with ProPlus’ DFY platform NanoYield for variation analysis with efficient process, voltage, and temperature (PVT) corner sampling, fast Monte Carlo or silicon-proven, high-sigma sampling with technology licensed from IBM.
When a large number of simulations are required, NanoYield enables near-linear scaling over multiple CPUs on a server or distributed computer farm, delivered through a cost-effective parallelization license model. The tight integration between NanoSpice and NanoYield can accelerate variation analysis to achieve the optimum yield versus power, performance and area trade-off by more than 20 times over using NanoYield with an external simulator.