Georgia Tech reports that is has won a 3-year, $2.9 million DARPA contract to develop 3-D chip cooling technology. The goal is to handle heat loads as much as ten times greater than those exhibited by today's chips while also handling on-chip hot spots that exceed even the 10X figure.
John Toon of the Georgia Tech news office quotes Yogendra Joshi, a professor in Georgia Tech’s Woodruff School of Mechanical Engineering and the project’s principal investigator, as saying, “There is really no good way to address this heat dissipation need with existing technology, and the problem is getting worse because computing power is increasing and the capabilities being put on chips are expanding. There is a real need for developing schemes that can address high power on the whole chip coupled with very high power dissipation areas that are only a few millimeters square.”
Challenges involve implementing nonuniform cooling using liquid evaporation, fabricating microfluidic cooling structures, and meeting reliability standards while ensuring that coolant vaporization within the structures does not induce dry-out, fluid leakage, or microfluidic passage cracking.
Indeed, reliability will be a big concern. Toon quotes Suresh Sitaraman, a professor in the Georgia Tech School of Mechanical Engineering and a member of the project team as saying, “The challenges for material characterization and physics-based modeling are to consider the larger features of the electronic system without overlooking the micrometer and sub-micrometer scale features that are the main locations for fracture and failure. Mechanical characterization and physics-based modeling will be important to understanding the reliability of microelectronic systems operating with fluid passages.”
Read more at Georgia Tech. For more on 3-D IC test and reliability, read these EE-Evaluation Engineering articles”:
- “Presentation at European 3D TSV Summit charts road to IC test“
- “Product Innovations Aid MEMS Design and Test“
- “Execs describe FormFactor's MicroProbe acquisition at ITC“
- “ITC topics extend from jitter measurement to board and system test“
- “3-D IC test workshop caps ITC activities“
- “Design for Test Tools Address Stacked Dies“
- “Charting the Design-and-Test Future“
- “Vendors Drive IC Advancements“
- “MEMS technology roadmapping could address test challenges“
- “Malefactors expected to attack 3-D ICs“
In addition, 3-D IC test is likely to be a topic of interest at the Test Vision 2020 Workshop to be held July 10-11, 2013, in San Francisco in conjunction with Semicon West.