GOEPEL and iSYSTEM Develop Integrated Validation and Test Platform
September 12, 2013. At the 2013 International Test Conference, GOEPEL electronic and iSYSTEM, a tool provider for embedded software design, announced the introduction of another new development within the framework of a long-term strategic cooperative effort for Embedded System Access (ESA) technologies.
The innovation named iTIC seamlessly integrates a complete on-chip debugger in the form of a TAP Interface Card (TIC) into the SCANFLEX ESA hardware platform for the first time. On this basis, it brings together technologies for nonintrusive software and hardware validation and test with unprecedented compatibility.
The iTIC, controlled via the TAP Interface Cards’ internal standard interface, supports all procedures for software debugging as well as any technologies for Embedded System Access, such as boundary scan, processor emulation test, FPGA-assisted test, and in-system programming of Flash and PLD.
“The new iTIC is a highly important milestone for the holistic implementation of our Embedded System Access philosophy. The successful cooperation with our long-term partner iSYSTEM enables us to support a considerably higher number of microprocessors and, furthermore, exploit synergies between different applications to an even greater degree,” said Thomas Wenzel, managing director of GOEPEL electronic’s JTAG/boundary-scan division. “The opportunity to execute all procedures on one platform brings users added efficiency in design validation and flexibility in test throughout the entire product life cycle.”
“In recent years, we systematically extended our tools‘ connectivity for embedded software development and test and associated partnerships with vendors of complementary products to create significant added values in operational efficiency and performance for our customers,” explained Erol Simsek, CEO of iSYSTEM AG. “Based on the intensive cooperation with GOEPEL electronic as market leader for Embedded System Access technologies, we will continue this course, and, additionally, extend our activities as OEM vendor.”
The iTIC is already the seventh member in the TAP Interface Card (TIC) family, controlled via a differential interface. That means all existing installations can be simply upgraded. The differential coupling enables trouble-free data transfer up to 80 MHz over distances of up to four meters. There will be no performance loss because runtime delays of cables, and units under test (UUT) can be individually compensated per TAP by means of the ADYCS technology. As a result, the iTIC can be integrated into application critical environments such as In-Circuit test fixtures.
Designed as an active test head, the iTIC supports a multitude of different operations and process architectures. These include standards such as IEEE 1149.1, IEEE 1149.6, IEEE 1149.7, IEEE 1532 and IEEE-ISTO 5001 as well as numerous non-JTAG interfaces like BDM (Background Debug Mode), SBW (Spy-Bi-Wire), and SWD (Serial Wire Debug). The target interface can be completely galvanically isolated via relays.
The iTIC is supported within SYSTEM CASCON and is automatically detected by the AutoDetect feature. Through OEM cooperation with all leading vendors of in-circuit testers (ICT), manufacturing defect analyzers (MDA), flying probers (FPT), and functional test systems (FCT), the new solution is available immediately for production test applications.