November 3, 2013. Reflex CES, a provider of modified-off-the-shelf (MOTS) solutions for embedded and complex systems, has announced the release of its new FPGA 64B/66B IP core. The turnkey solution can accommodate the Xilinx Aurora protocol, enabling designers of complex systems to interconnect Xilinx and Altera high-speed transceiver FPGAs. Based on Altera FPGAs, the new IP core supports 64B/66B encoding and high-speed interfaces up to 14.4 Gb/s, enabling interoperability between Xilinx and Altera FGPAs, with an effective bandwidth of up to 97%.
Targeted specifically at complex, embedded military and telecommunications networking applications, the 64B/66B FPGA IP core allows designers to choose the most appropriate FPGA solutions to meet their needs, from single or multiple vendors.
“In a complex system with mixed FPGAs, it is always difficult to find a turnkey solution which effectively manages communications using high speed transceiver links,” noted Sylvain Neveu, Reflex CES co-founder and COO.
“With this new IP in our portfolio, engineers are assured interoperability between all leading FPGAs, whatever the performance of their backplanes and systems, from 1 to 14 Gb/s, and whatever the generic or configurable features incorporated,” he added.
The new IP core offers a fully compliant implementation of the Xilinx Aurora 64B/66bB scalable, link-layer protocol for high-speed serial communication, and it allows for communication between FPGAs through a backplane. Based on this open standard protocol used to transport data with higher connectivity performance for chip-to-chip and board-to-board architecture, the Reflex CES Aurora-compliant 64B/66B IP core allows designers to move data from point-to-point across 1 to 16 serial lanes at up to 14.1 Gb/s.
The core features user flow control, native flow control, immediate and completion mode, as well as modules to convert interfaces to and from streaming Advanced eXtensible Interfaces (AXI). This low-protocol-overhead IP core offers customers minimal data rate transfer latency with minimal logic resources (900 equivalent logic cells for a 4 lane configuration in simplex mode) for cost effective implementation.