ITC panel: should analog DFT be digitized?

Seattle, WA. The International Test Conference got off to an enthusiastic start this week with a Monday evening panel discussion entitled “Analog Design for Test: What’s the Real Story?” My takeaway is that there is not one “Real Story.” Your story depends on factors unique to you, such as application, wafer size, die size, time to market pressures, product life expectancy, analog/digital mix, and packaging cost.

ITC panel opinions are, as the program committee puts it, “…in the formative stage and do not represent completed work or the official position of the speaker or of his or her company.” Comments are “not for quotation or attribution,” so if you weren’t there, you won’t know who said what. (There are additional panels scheduled for ITC that you can still attend and learn who said what.) Nevertheless, many themes emerged that are worth considering.

But first, it’s worth noting that the panel included about equal representation of the design and test communities. Given a choice between design or test, an overwhelming percentage of audience members identified with test, although a seemingly similar percentage identified with design-for-test when given that option.

So here are a few general takeaways based on comments from the panelists and the audience (keep in mind that some comments were serious, some facetious, and some deliberatively provocative):

Designers are not implementing the analog DFT techniques presented at ITC because designers do not attend ITC and read the relevant papers.
Papers on analog DFT are not necessarily completely relevant to analog circuit designers’ specific test challenges. (I’m interpreting this contention as expressed in the discussion very politely.)
Designers lack commercial analog-fault-simulation tools—they have relatively low analog fault coverage but don’t know that.
Self-healing and self-calibration techniques don’t represent a general solution for analog DFT (as do ATPG and scan-pattern compression in the digital realm)—every analog design is different.
Analog DFT papers emphasize the “big 4”: ADCs, DACs, PLLs, and SerDes. For other mixed-signal functions, you might waste six months of development time to shave 30 ms off a total 50 ms test time—it’s just worth it.
Just digitize everything at the input pin and be done with it already—then the mostly-all-digital chip can be designed and tested using well established digital DFT techniques.
Get over it, the world is analog.
Test and DFT engineers might be correct in asserting the importance of analog DFT, but they are not becoming more popular by suggesting designers take on more test tasks.
Management must assert the benefit or lack thereof of analog DFT.
Lack of communication between design and test engineers is a recipe for failure.
Potential loading and mismatch issues surrounding the effect of analog DFT on analog-circuit performance discourage analog DFT’s use.
Pins are precious, and I/O pins dedicated to analog test are not acceptable.
If a lack of analog DFT is such a big problem than why does my analog/digital/RF cellphone work so well?
Analog failures account for a large percentage of field returns.
Analog circuits don’t need DFT because they occupy relatively large amounts of silicon real estate and are less prone to failure than are bleeding-edge sub-20-nm digital devices.
With better analog DFT, analog functions wouldn’t require so much real estate and we could get more of them on a chip.
It’s mostly input-noise issues, not other issues, that determine analog-circuit real-estate requirements.
The importance of analog DFT depends on whether you are making a “big D little A” chip (maybe 4% analog) or a “big A little D” chip (50% analog).
Tester makers sincerely hope designers don’t incorporate more analog DFT.
Mixed-signal IC makers may be willing to add the occasional analog-DFT-dedicated MCU block to an IC to obviate the need for a $2 million tester.
MCU makers are happy to have their IP added to an IC for analog-DFT purposes.
Test within an analog, digital, or RF block is not sufficient—it’s the interaction of the blocks that counts.
Digital is becoming the new analog, and analog is becoming the new digital, so let’s not jump to any conclusions.