Averna completes DOCSIS 3.1 interoperability test

Dec. 19, 2014

Averna announced it has successfully participated in the first interoperability test of DOCSIS 3.1 products organized by CableLabs. In combination with other vendors’ DOCSIS 3.1 equipment, Averna’s DP-1000 DOCSIS protocol analyzer successfully performed OFDM downstream capture at the event.

This DOCSIS 3.1 interoperability event included providers of early implementations of cable modems, CCAPs, and test and measurement equipment. The goals of the event were to test product interoperability and successfully demonstrate both higher efficiency and wider channels, which combine to make multi-Gb/s speeds possible.

“We are extremely proud of our achievement at this first DOCSIS 3.1 Interop. Our DP-1000 was among the first commercially ready products that successfully performed DOCSIS 3.1 OFDM downstream capture at the event,” said Alex Pelland, director of broadband test strategy for Averna. “This is an important milestone for Averna as well as for the industry and we congratulate all the participants.”

Co-developed with major industry players and designed for both DOCSIS 3.0 and 3.1, the Averna DP‑1000 DOCSIS protocol analyzer is used to analyze, debug, maintain, and monitor local networks and Internet connections. Multiple systems operators (MSOs), chipset manufacturers, product developers, and certifications bodies can use it to quickly find and correct trouble spots in order to maintain the highest quality of service possible.

Optimized for real-time signal processing with FPGA technology, the DP-1000 analyzes up to 32×8 single or bonded US/DS channels (DOCSIS 3.0) and 2×1 OFDM US/DS channels (DOCSIS 3.1), and it includes numerous channel-filtering, demodulation, triggering, display, and upgrade features.

As a passive sniffer between CMTS and CPE devices, the DP-1000 silently captures and filters DOCSIS MAC-layer data in real-time to verify RF parameters, validate MAC-level communication, troubleshoot interoperability issues, and improve network performance.

www.averna.com

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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