Intellitech brings IEEE 1149.1-2013 IP block verification to Synopsys VCS
Dover, NH. Intellitech Corp. has announced interoperability between its NEBULA silicon debugger, the Intellitech iJTAGServer bridge, and the Synopsys VCS functional-verification environment. The integrated solution enables IP providers to develop and validate computer-readable IEEE-compliant descriptions for Silicon Instruments, the IP blocks in an SoC that are accessible via IEEE 1149.1/JTAG. These IP blocks enable critical on-chip configuration, monitoring, and test throughout the life-cycle of an SoC. PVT (process-voltage-temperature) monitors, SerDes analog parameters, electronic-chip IDs, PLL control, and memory BISRs (built-in-self-repair) are a few examples of Silicon Instruments that are used during first silicon bring-up, production IC test, or with the IC in-situ on a PCB (printed circuit board).
Silicon Instrument documentation is developed using Intellitech’s NEBULA software as a front end, and the Synopsys VCS verification environment provides the expected responses and code coverage metrics. NEBULA reads IEEE 1149.1-2013-compliant IP models that describe the Silicon Instrument abstractly and uses 1149.1 PDL (Procedural Description Language) to perform transactions to and from the instrument in simulation as would occur in a real SoC. IEEE 1149.1-2013 PDL is used as a complement to SystemVerilog. 1149.1 PDL has specific capabilities targeted for JTAG accessible Silicon Instruments that SystemVerilog can’t achieve. Once PDL for a Silicon Instrument is validated using Synopsys VCS, the same PDL documentation can then be re-used by the SoC integrator and the ATE engineer without concern for the documentation correctness or robustness of the verification. That same instrument PDL can also be re-used by the system company using the SoC to talk to the instrument for board test or test in the field.
“Synopsys has a long history of advancing product interoperability through standards bodies as well as programs of our own, such as in-Sync,” remarks Karen Bartleson, senior director of Corporate Programs and Initiatives at Synopsys, Inc. “Through in-Sync, Intellitech can help our mutual customers meet their IEEE 1149.1-2013 based verification needs.”
“We are pleased to be a member of Synopsys’ in-Sync Program,” said CJ Clark, Intellitech’s chief executive officer. “Through Synopsys’s keen insight on the benefits of interoperability, we were able to develop a PDL bridge to VCS for our mutual customers to perform metric-driven instrument verification. For the first time in the industry, customers of instrument IP can not only contractually specify IEEE 1149.1-2013 compliance, but also require pre-validated IEEE 1149.1-2013 documentation and code coverage metrics from their IP provider. The SoC integrator can then take this pre-validated documentation and use it directly on ATE, avoiding the costs of re-interpretation of the IP provider’s test vectors and instrument intent. The time to validate instrument operation and descriptions is not post-silicon on the IC tester; that adds risk, schedule impact and ultimately cost,” he noted.
As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system, and manufacturing challenges. Through the in-Sync program, Synopsys promotes interoperability between its tools and other EDA companies’ tools to help mutual customers meet their stringent design flow requirements.
Intellitech is an industry leader in ATE for test and silicon debug of IEEE 1149.x-based products. The company is sought out by customers to provide methodologies, IP, and tools which lower a customer’s cost in developing or manufacturing an electronic product.
