Test magic descends on Disneyland with ITC

The International Test Conference gets underway at the Disneyland Hotel Conference Center in Anaheim, CA, this week. An opening keynote address, two additional addresses, a poster session, and three panel discussions will complement the event’s extensive technical program, which offers up to 80 presentations. In addition, companies will be on hand to demonstrate their latest hardware and software technologies.

In addition, three workshops will follow the main conference:

• “3D-TEST: 6th IEEE International Workshop on Testing Three Dimensional Stacked ICs”;
• “TVHSAC: 4th IEEE International Workshop Test & Validation of High Speed Analog Circuits”; and
• “DATA: IEEE Workshop on Defect and Adaptive Test Analysis.”

According to Douglas Young, general chair, and William Eklow, program chair, “ITC covers the complete cycle from design verification, design-for-test, design-for-manufacturing, post-silicon validation and debug, manufacturing test, diagnosis, failure analysis and yield improvement, system testing at the hardware-software interface, error detection and testing in the field (including adaptation to variations induced by manufacturing and operating conditions), hardware security and trust, then all the way back to process and system design improvements.”

Karim Arabi will deliver the keynote speech at the ITC Opening Plenary Session at 9 a.m. on Tuesday October 6. The title of his speech will be “Brain-inspired Computing.” Arabi is vice president of engineering at Qualcomm, where he is responsible for research and development in ASIC and new product development. Previously, he was VP, engineering and technology, at Dialog Semiconductor responsible for driving overall technology and new product development. He also held technical positions at PMC Sierra and Cirrus Logic and was cofounder of Opmaxx, a startup that focused on analog design and test.

On Wednesday, Andrew B. Kahng in an address titled “Modeling the Future of Semiconductors (AND TEST!)” will comment on the semiconductor products that will drive manufacturing and test technology over the next 10 to 15 years. Kahng, a professor at the University of California at San Diego, will discuss heterogeneous integration and “More than Moore” scaling.

And on Thursday, William R. Bottoms, chairman of Third Millennium Test Solutions, will deliver a talk titled “Can We Ensure Reliability in the Era of Heterogeneous Integration?” He will focus on quality in an era when devices include active photonics, electronic, and plasmonic components as well as passive devices, RF sensors, and MEMS.

ITC will also include three panel sessions to complement the technical program. The first, scheduled for 4:45 p.m. Monday, is titled “Is IEEE 1149.1 on Its Death Bed?” Kenneth Posse of Avago Technologies will serve as moderator. Panelists include Jason Doege, Centaur Technology; Jeffery Rearick, AMD; Teresa McLaurin, ARM; and Zoe Conroy, Cisco Systems. That panel will be followed by a reception.

The second panel, scheduled for 10:30 a.m. Wednesday, is titled “Cell-aware ATPG: Beyond the Hype.” The moderator is Robert Aitken of ARM; organizers are Erik-Jan Marinissen of imec and Sandeep Goel of TSMC. The panelists are Jeff Block, DCG Systems; Stefan Eichenberger, NXP Semiconductors; Sandeep Goel, TSMC; Friedrich Hapke, Mentor Graphics; and Peter Wohl, Synopsys.

The final panel is scheduled for 2 p.m. Thursday and is titled “Big Data for Test—Big Opportunity or Big Mystery?” panel organizer and moderator is Li-C. Wang, University of California at Santa Barbara. The panelists are Kenneth Butler, Texas Instruments; Xinli Gu, Huawei Technologies; Michael Laisne, Qualcomm; Phil Nigh, GLOBALFOUNDRIES; and Srikanth Venkataraman, Intel.

Several companies have indicated their plans for ITC. Mentor Graphics will offer theater presentations featuring customers and partners during exhibit hours, and the company’s Steve Pateras will present a corporate vendor forum session titled “Test Solutions for the Automotive Market” 1:40 p.m. Wednesday.

Synopsys will hold its 23rd Annual Test SIG Event at ITC at 6:30 p.m. Monday. Test experts from leading companies will describe how they are using the Synopsys synthesis-based test solution to test FinFETs, meet challenging ISO 26262 automotive requirements, and implement hierarchical test of SoCs. Speakers include Leah Clark, Broadcom; Davide Appello, STMicroelectronics; Jon Colburn, NVIDIA; Marc Hutner, Teradyne; and Peter Wohl, Synopsys.

On the exhibit floor, Synopsys will highlight ATPG technology for testing FinFET logic and memory circuits and in-system self-test for meeting stringent functional safety standards for automotive and other applications. The company will demonstrate slack-based cell-aware technology for FinFET testing that uses detailed timing information from PrimeTime to achieve high coverage, standards-based hierarchical SoC test for simultaneously implementing logic BIST and memory BIST, and comprehensive RTL testability analysis.

Members of Cadence’s R&D team will be on hand to share updates on how customers are using the company’s differentiated design-for-test (DFT) capabilities within Cadence Genus Synthesis Solution cockpit, Cadence Encounter True-Time ATPG, and Cadence Encounter Diagnostics.

Optimal+ will be showcasing its big data solutions that enable fabless companies and IDMs to manufacture intelligence from their semiconductor operations.

The company also invites attendees to hear Marc Jacobs, VP of engineering operations, Marvell Semiconductor, discuss Marvell’s success with Optimal+ in its manufacturing operations. Jacobs’ presentation is set for 11 a.m. to 1 p.m. Wednesday. Lunch will be served.

Astronics will present its latest test systems and capabilities for the semiconductor, aerospace, and defense electronics industries. The company’s integrated test systems feature hardware and robotics plus a suite of IDE and runtime test software. The company reports that it has tested more than 5 billion devices.

ASSET InterTech will also be exhibiting; Tim Caffee, ASSET’s vice president for design verification and test, will be explaining the differences between traditional “1 x 1” pass/fail validation testing and the “N x N” statistical validation methodologies that chip suppliers like Intel and others are recommending.

Test Insight will describe how to make it easy for test and DFT engineers to translate complex design data into high quality ATE patterns, how to cut down on the amount of simulation required to create test patterns, and also how to get more commonality between silicon validation and production test.