VTS 2016 submission deadlines are approaching

Oct. 13, 2015

The 34th IEEE VLSI Test Symposium (VTS 2016) is set for April 25-27 in Las Vegas, NV, and key submission deadlines are approaching. Abstracts are due October 16, and full PDF submissions are due October 23. Notification of acceptance will be provided December 20.

The IEEE VLSI Test Symposium explores emerging trends and novel concepts in testing, debug, and repair of microelectronic circuits and systems.

Major topics include but are not limited to

  • analog/mixed-signal/RF test,
  • ATPG and compression,
  • ATE architecture and software,
  • automotive test and safety,
  • built-in self-test (BIST),
  • defect and current based test,
  • defect/fault tolerance,
  • delay and performance test,
  • design for testability (DFT),
  • design verification/validation,
  • embedded system and board test,
  • embedded test methods,
  • emerging technologies test,
  • FPGA test,
  • fault modeling and simulation,
  • hardware security,
  • low-power IC test,
  • microsystems/MEMS/sensors test,
  • memory test and repair,
  • on-line test and error correction,
  • power/thermal issues in test,
  • system-on-chip (SOC) test,
  • test standards,
  • test economics,
  • test of biomedical devices,
  • test of high-speed I/O,
  • test quality and reliability,
  • test resource partitioning,
  • transients and soft errors, and
  • 5D, 3D, and SiP test.

Visit the symposium website for detailed instructions for submissions.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!