Requesting input on high-speed-digital design and test

Oct. 24, 2016

DesignCon will take place January 31 through February 2 in Santa Clara. As of today, organizers are expecting that the exhibit floor will offer attendees the opportunity to meet with 185 vendors, while the technical program will offer more than 100 technical paper sessions, panels, and tutorials in 14 tracks.

EE-Evaluation Engineering’s January issue will include a special report on high-speed-digital design and test, with a focus on next-generation interfaces, including USB and PCIe as well as ones defined by MIPI.

If you will be exhibiting at the show, please help us provide our readers with a preview of your highlights by answering the following questions:

  1. What design, simulation, and test solutions will you be highlighting at DesignCon 2017?
  2. What solutions do you offer for the design and test of next-generation high-speed serial interfaces (such as USB, PCIe, memory interfaces, and ones defined by MIPI)?
  3. What is unique about your solutions covered in questions 1 and 2, and what problems do your solutions help customers solve?

If you will be attending DesignCon, let us know what you would like to see from exhibitors.

Please respond to [email protected] by November 1. Thanks.

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