Map JTAG Technologies test access with Altium Designer

Nov. 9, 2016

Eindhoven, the Netherlands. JTAG Technologies has introduced its new collaborative product with Altium—JTAG Maps.

A large number of today’s electronic designs feature JTAG/boundary-scan components that provide valuable test resources during hardware debug, manufacturing test, and even depot repair. JTAG Maps is a simple extension to the Altium Designer tool suite that allows engineers to thoroughly assess the capabilities of the JTAG/boundary-scan resources on their design—before committing to layout.

Until now engineers could often spend hours highlighting the boundary-scan nets of a design manually to assess the fault coverage that boundary-scan testing could bring a specific design. Today the free JTAG Maps for Altium application extension does all this and more, freeing up valuable time, allowing a more thorough DfT and speeding time to market.

Boundary-scan device models (BSDLs) are pivotal to any JTAG/boundary-scan process as they indicate precisely which pins can be controlled or observed by JTAG/boundary-scan. However BSDL models are not always available in a timely manner. To overcome this potential problem JTAG Maps for Altium includes an “assume scan covered” feature enabling a view of potential boundary-scan coverage without a specific BSDL. This feature can also be used to indicate fault coverage to a connector (set to assume scan covered) or to highlight the differences in fault coverage between two equivalent parts, one with and one without built-in JTAG/boundary-scan.

JTAG Maps for Altium will automatically detect the scan-chain path (or paths) with no limits to the number of paths (aka TAPs) in the design. The nets associated with the TAPs will be highlighted separately from the “testable” nets using different colors.

While most users will want to simply use the quick coverage report that JTAG Maps for Altium can provide, it is still possible to import a more accurate picture.

After exporting a JTAG ProVision project, the data can be sent to your local JTAG Technologies office, Approved Application Provider, or approved JTAG representative for further analysis. A simple message file containing full fault-coverage information can then be read back into JTAG Maps for display/highlighting.

For engineers wishing to apply JTAG/boundary-scan tests directly onto their design JTAG Technologies can offer two further options, JTAG Live for low-cost functional testing with boundary-scan and JTAG ProVision, a full-blown automated test program generation and device programming system.

www.jtag.com

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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