Fort Worth, TX. Board- and system-level test was the focus of a Monday tutorial at the International Test Conference. Krishnendu (Krish) Chakrabarty offered a presentation titled “Test, Diagnosis, and Root-Cause Identification of Failures for Boards and Systems,” developed by him and Bill Eklow, who was unable to attend. The tutorial described board- and system-level test challenges and why chips that pass ATE test can fail in boards and systems, and it proposed machine-learning techniques to address the challenges.
Chakrabarty described the consequences of inappropriate or inadequate test: long test times, excess inventory, unhappy customers, and shipments held up as stock prices go down. There is a gap between working silicon and working boards and systems, he explained, resulting in system-level failures that are subtle and difficult to debug. He cited several problems, including a lack of effective feedback among globally dispersed chip, board, and system vendors. (For one potential solution to this problem see “OCMs, OEMs sharing data creates a win-win.”)
Board and system test, of course, determines whether the boards and systems are assembled correctly and that interconnect functions properly. Tools such as boundary scan can help. However, even with correct assembly, boards and systems populated with semiconductors that passed ATE tests can fail. Systems are sets of interacting components, Chakrabarty said, and a functional-system-test specification can run 1,000 pages. Further, systems of systems impose a system hierarchy, with an additional layer of complexity.
So why might a chip that passed manufacturing test cause board or system failures? The tester environment includes a low-noise DUT-board design, controlled stable temperatures, and accurate power supplies, Chakrabarty said, adding that the noisy, complex, multiple-component board or system environment is hard to map onto ATE. For example, the chipmaker developing the manufacturing test usually won’t even know what additional chips its product will be interacting with in the real world. Porting the system-test environment to ATE is easier said than done, he said.
What can be done? Data gathering is key, Chakrabarty said, often assisted by DFT—status and error registers as well as monitors (logic analyzers, oscilloscopes, and temperature and voltage monitors). Simulation and fault-insertion can also play a role, as can BIST.
After data is gathered, it must be analyzed. Options, Chakrabarty explained, include rules-based decision-making (involving a fault decision tree), knowledge-based diagnosis (involving a fault dictionary), and reasoning-based diagnostics.
These approaches have drawbacks, Chakrabarty explained. For example, a fault-decision tree can grow exponentially and is unlikely to ever be exhaustive. It can lead to “rule aliasing” that leads you toward fixing the wrong problem.
Chakrabarty’s approach to the problem is a diagnosis system employing AI-based machine learning to alleviate problems related to low yield, high return rates, long debug times, and high repair costs. He has investigated both support vector machines and artificial neural networks, which can learn from empirical data to make intelligent decisions. He recounted experiments with more than a thousand industry boards that had failed tests—811 of which were used in training an artificial neural network, and 212 of which were used to evaluate the effectiveness of derived test strategies. He reported that the ANN results exceeded those of traditional methods employed by the manufacturers.
