What you’ll learn:
- Why there’s a need for PCIe supplemental tools to rapidly increase time-to-market for cutting-edge innovations.
- What tools are currently available to provide solutions for PCIe validation issues among macrotrends?
Less than 20 years since the PCI Express (PCIe) 1.0 specification was introduced by the PCI Special Interest Group, the industry is already preparing for PCIe Gen 6.0. With each new generation of the standard doubling the data rate of the previous generation, PCIe Gen 6.0 is more than 25X faster than the original PCIe Gen 1.0 specification introduced in 2003.
This doubling of data rates every three years has introduced countless challenges for validation engineers responsible for the physical-layer performance of their PHYs, chips, cards, and systems. And not all are being fully addressed by testing equipment available today.
While most of these challenges have been addressed by the increasing performance of key electrical validation equipment like oscilloscopes and BERTs, these performance improvements also have impacted testing complexities in setup and equipment usage. In turn, it has contributed to increased testing and debug times for validation teams.
It’s a natural progression that test-equipment performance exceeds that of the standard it sets out to validate. However, some of the other challenges faced by engineers aren’t being fully addressed with test-equipment performance improvements alone.
Engineers today need tools that complement the performance of existing equipment by providing faster time-to-insight and superior ease-of-use, while not significantly impacting capital budgets for their projects. A case for each of these needs can be made by looking at industry macrotrends.
Time-to-Market Challenges: The Case for Faster Time-to-Insights in PCIe Testing
Because the latest PCIe standards must support all previous PCIe generations, the testing matrix for each new PCIe generation grows exponentially for validation teams. This, coupled with the mounting testing complexities as the standards progress, has significantly increased overall testing times for programs working to implement the latest PCIe standards. What further complicates the situation is the expectation that these teams produce next-generation products in a similar time-to-market window as previous generations.
Evaluating link performance and debugging problems takes longer than ever. Unfortunately, the equipment available today doesn’t support engineers in a way that saves them days or weeks of debug and performance evaluation necessary to support these timelines. There will always be a need for high-performance tools like oscilloscopes and BERTs that focus on pushing performance boundaries, but the industry needs a new tool in the tool bag.
The modern engineer needs a new category of test and measurement equipment that’s easier to set up and use. It also must deliver faster time-to-insight to allow for more frequent testing during design and validation to identify issues earlier in the development cycle.
Expected Labor Gap: The Case for Ease-of-Use in PCIe Testing
As the digital world becomes more deeply ingrained in everyday life, the demand for semiconductors and semiconductor devices continues to grow exponentially. This parabolic growth has most notably led to major challenges for the industry in terms of supply chain and logistics.
What is less-often discussed, and what may be most concerning, is the expected shortfall in the engineering workforce to support the growth. According to a presentation from the 2022 SEMICON West conference, by 2030 there will be an expected deficit of approximately 300,000 engineers needed to support the growth of the semiconductor industry. This deficit is largely attributed to fewer new college graduates transitioning into the industry and the expected attrition from the ranks over the coming years.
This is a significant complication for companies in the industry, and one that’s not easily solved due to the technical nature of development and validation of high-speed I/O (HSIO) devices. PCIe, in particular, is positioned to grow increasingly complex as successive generations of the standards are released. The workforce gap to support development and validation of these devices is expected to put further stress on program timelines and testing workflows for engineering teams across the industry.
To address this expected labor gap across the industry, companies may be required to assign engineering tasks more broadly than in the past, creating a need for testing equipment that’s easier to set up and operate than existing solutions. As this macrotrend unfolds, it will become ever-more important to have equipment that requires less training and expertise to operate, yet still provides meaningful insights into the health and performance of HSIO devices.
Monetary Scrutiny: The Case for Capital Budget Optimization in PCIe
As data rates have risen for subsequent standards of PCIe, so has the demand for higher-performance equipment. The bandwidth requirements needed to support this equipment continues to expand, and with that performance comes significant cost for acquiring full testing suites. These costs are so significant that even larger companies are often in a position to purchase only a few complete systems.
Smaller companies see an even greater impact. They often can’t afford the equipment needed for complete validation testing, and instead must rent or use third-party testing facilities to conduct their validation and debug.
Because performance is paramount for full PCIe evaluation and compliance testing, companies must absorb significant equipment costs to perform testing, whether they choose to purchase or rent. While there’s no way to avoid this entirely, equipment that can provide meaningful insights into designs earlier and faster without putting significant strain on capital budgets for programs will more readily become a welcome solution.
Having equipment that can accelerate testing by increasing the number of test setups and reducing overall testing times, without putting significant strain on program budgets, prepares engineering teams to efficiently use the higher-performance equipment when needed.
Answering the Call: A New PCIe Test and Measurement Solution
There will always be a need for high-performance validation and compliance testing equipment, but equipment that can accelerate time-to-insight, is easy to use, and is cost-effective, will be a vital complementary solution to the existing tools in the testing workflow for PCIe today. Through the deep understanding of industry needs, the TMT4 Margin Tester developed by Tektronix is the first and only supplemental solution on the market to help address key macrotrends for PCIe Gen 3 and Gen 4 testing.