DDS Basics

June 26, 2008
Most newer signal generators, such as arbitrary waveform generators (AWGs), lower-frequency RF generators, and vector signal generators (VSGs), use direct digital synthesis (DDS) instead of fractional-N phase-locked-loop (PLL) synthesizers, which are c

Most newer signal generators, such as arbitrary waveform generators (AWGs), lower-frequency RF generators, and vector signal generators (VSGs), use direct digital synthesis (DDS) instead of fractional-N phase-locked-loop (PLL) synthesizers, which are common in older instruments and higher-frequency RF generators.

Though not new, DDS has improved significantly over the past few years thanks to the arrival of faster, single-chip DDS synthesizer chips like those from Analog Devices (Fig. 1). The basic technique uses the architecture shown in Figure 2.

The simplest form of address generation uses a counter to access the samples in the memory, which are then sent to a digital-to-analog converter (DAC) that produces the sine output. This works fine, but the output frequency (fO) depends on the counter clock frequency (fC) and the number of sine samples (M) in RAM or fO = fO/M.

This means the clock frequency must be very high to produce even a low-frequency output. Also, you must change the clock frequency to change the output frequency, which doesn’t make it easy to get crystal accuracy or stability.

A DDS uses this same waveform-generation method, but replaces the counter with a sophisticated phase accumulator circuit as shown in the figure. A clock signal from a crystal-based oscillator clocks the adder and output address register/accumulator that feeds the address to the DAC.

The address register output is added to a phase register value to get the next ROM address value. By changing the phase register value, which comes from a processor or other circuit, the phase increment of the output is changed. To alter the frequency, you change the phase register value (C) or:

fO = C(fC)/2N

Here, N is the number of bits in the phase register.

DDS ICs are available with clock input values to 1 GHz and with phase increments of 24, 32, or 48 bits. This provides 2N phase resolution for 360°. DAC update rates are also available to 1 GHz with output bit resolutions of 10, 12, and 14 bits. Thus, DDS synthesizers can produce outputs in the hundreds of megahertz range with very high frequency and phase increment precision. Also, DDS ICs are available with AM, FM, and PM modulation, as well as two channels for producing I and Q signals with high 90° separation precision.

DDS synthesizers offer the benefits of high frequency and phase resolution, plus the ability to change frequency in nanoseconds versus the microseconds or more that’s typical of PLL synthesizers.

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