Electronic Design

DTF And ATPG Enhancements, Improve Compiler Performance

A series of design-for-test (DFT) and automatic pattern generation (ATPG) products leverage advanced test modeling for dramatic capacity and performance gains in Synopsys' DFT Compiler. The TetraMAX ATPG delay test option's comprehensive capabilities help designers detect timing-related defects during manufacturing test.

The new test modeling technology supports advanced hierarchical DFT flows in the company's physical synthesis environment, which increases the tool's capacity more than threefold. It also increases speed sevenfold with no impact on the product's ability to implement timing- and layout-optimized DFT.

TetraMAX DelayTest offers a structured, scan-based approach to delay testing. It provides predictable and measurable delay test coverage and ensures compatibility with low-cost ATE. It permits designers to easily create test patterns for the most common timing-related defect models--transition delay and path delay faults.

Current DFT Compiler customers will receive the new capability at no extra charge as a maintenance update. Pricing begins at $22,500 for a one-year technology subscription license (TSL). The DelayTest option to TetraMAX ATPG costs $36,660 for a one-year TSL.

Synopsys Inc.
(650) 962-5000; www.synopsys.com

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.