EDA Update: 90-nm X Architecture Test Chip

Nov. 24, 2003

A functional 90-nm X Architecture test chip has emerged from Toshiba's fab. Compared to a Manhattan version of the same design, the five-metal-layer test chip requires 14% less total wire length and 27% fewer vias. The chip is fully functional at its specified operating frequency. Having completed its pre-production roadmap, the X Initiative will now turn its attention to enabling broad adoption of the X Architecture. Learn more at www.xinitiative.org.

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.