Reaching a significant milestone, Accellera's board and technical committee members approved four new standards for language-based design verification. Key EDA vendors have already gotten behind the standards as Accellera prepares for the next step: submission of the standards to the IEEE for standardization in the IEEE 1364-2005 version of Verilog.
The four new standards are the Property Specification Language (PSL) 1.01, the Standard Co-Emulation Application Programming Interface (SCE-API) 1.0, SystemVerilog 3.1, and Verilog-AMS 2.1. According to Accellera chairman Dennis Brophy, committee members will reconvene during the summer to review comments on the standards.
To enable open interoperability for next-generation IEEE Verilog, Cadence Design Systems donated comprehensive and portable Verilog language extensions to the IEEE, driven by customer requests. These include a universal testbench implementation for all IEEE 1364-compliant Verilog simulators. In addition, Cadence announced comprehensive support for the IEEE 1364-2001 standard within the Cadence Incisive verification platform.
According to Mitch Weaver, Cadence's VP of marketing for verification products, the company defines "next-generation Verilog" as "whichever one the IEEE gets behind." Accellera's approval of SystemVerilog 3.1 and its commitment to hand it off to the IEEE quickly is reason to applaud, he said.
Some within the EDA industry have expressed fears that a split within vendor ranks would ultimately lead to a bifurcation of Verilog standards. But so far, some of the industry's largest vendors have expressed support for Accellera's move to take SystemVerilog 3.1 to the IEEE.
"There is only one Verilog," says Weaver. Rich Goldman, VP of strategic market development at Synopsys, echoed, "We will not end up with competing versions of Verilog. We expect the IEEE to do the right thing. Customers clearly want SystemVerilog 3.1. This will show through in the standardization of SystemVerilog 3.1 in the IEEE."