Assertion-based simulation and verification is touted as a way to greatly accelerate detection and elimination of errors in IC designs. After months deliberating, the Accellera Formal Verification Technical Committee has endorsed IBM's Sugar 2.0 formal property language as a standard language for formal properties. This move could lead to widespread adoption of assertion-based verification.
A raft of electronics and EDA companies quickly lined up behind the choice, saying that adoption of Sugar as a standard formal property language would be a key in promoting EDA tool interoperability. Accellera and the companies supporting the standard expect Sugar 2.0 to improve tool interoperability and enhance the simulation and functional verification processes.
Sugar 2.0 enables designers to capture specifications, requirements, and assumptions as assertions about the hardware description language (HDL) description of a digital IC design. These assertions can then be verified through simulation or formal verification.
The next step in the standardization process, says committee chair Harry Foster, is to turn the Sugar 2.0 specification into a Language Reference Manual for the Accellera board's approval. This is expected to be accomplished within the next few months.
In related news, Synopsys recently delivered version 2.0 of the open-source OpenVera verification language with new additions to OpenVera assertions based on Intel's ForSpec language. The Intel/Synopsys axis is attempting to forge support within the industry for OpenVera as a competing assertion-language standard in its own right. Verplex Systems, @HDL, and Novas have hedged their bets by supporting OpenVera as well as Sugar.
