Like their analog-to-digital converter (ADC) counterparts, digital-to-analog converters (DACs) are moving toward higher speeds and resolutions at a lower operating power. The primary drivers are higher speed, greater resolution, and lower power. Moreover, higher integration is taking place among DACs, with digital error correction and post processing now included.
Bit resolution is increasing from a median of 8 bits to higher bit counts, reaching a plateau at about 14 bits. Most users don't go above 14 bits because the board layout is more critical and because the system can't use any additional bits. The noise floor and dynamic range of the converter dominate bit resolution. Thus a drop in supplies, caused by digital parts moving to smaller process geometries, reduces the possible dynamic range and increases the sensitivity to noise.
Resolution increases require more internal devices, but the higher speeds tend to force reductions in bit counts due to internal capacitance. For very high speeds, amplifiers and other internal components will need to go to an SOI-type process to minimize device parasitic elements.
Converters are moving toward more bits and higher speeds. In these areas, the drivers parallel the digital world by going to smaller feature sizes for higher levels of integration. Yet unlike their ADC cousins, the D/A parts are already in the best technology. The processes don't stand in the way of better performance, but the devices won't lead the move into the next smaller process generation. The parts aren't process-limited, although the output voltage must be within less than 1-LSB accuracy of an absolute value on the output. ADCs can scale the input voltage for any reasonable range either internal or external to the chip.
Precision is adequate in the low-cost areas. The string DAC architecture is now available in single, dual, and quad configurations, and they ship for less than $2 in quantity. The architecture sacrifices internal linearity, but this is acceptable in the common control loop or calibrated sensor applications. Usually the sensor has a greater error budget than the converter, so the converter need only be monotonic.
A smaller die tends to imply lower power, but the form factor also is shrinking. The challenge is to make the design faster with lower power at the same time, so the thermal resistance isn't an issue in use.
Even though the shift is on to smaller packages, DAC functions are becoming more highly integrated. DACs are moving toward maximizing the number of parts in the package. Whole subsystems can include buffers and may even incorporate other types of converters and interfaces into the rest of the system. One ongoing change is to have differential signal paths for a higher dynamic range and higher speeds in the signal chain.
>HIGH-RESOLUTION DACs will go to 18 bits, which is already common for the analog-to-digital converter (ADC). The digital-to-analog converter (DAC) must move up to continue as part of a matched set. Further increases in resolution beyond 18 bits will take much greater effort in system-level design, which may not be worth the additional effort in the pc-board and interconnect designs.
>THE COST OF THE HIGH-VOLTAGE (±10-V) parts will track the rest of the products, so higher supply voltage won't cost a premium. The continuing existence of separate, high-voltage analog sections will continue to drive the bifurcation of supplies, as the designers start to look for better system performance as compared to power-supply compatibility.
Look for some very high supply voltage parts for 42-V automotive applications. The auto market is already moving the system supply from 12 to 42 V in some of the high-end vehicles. The auto makers are reluctant to add one more power supply to their systems, but they still need high accuracy and high noise rejection in the components they use for systems.
>THE NUMBER OF CONVERTER TYPES and capabilities will continue to increase, with the set of all possible parts numbers significantly growing. Just as in the amplifier area, application-specific converters will proliferate with many variations within a set of speeds and bit resolutions. The wide range of applications means that the "best" converter will always contain specifications that don't exist within a single IC.
Multichannel ADC and DAC reside on a single chip, with both types of converter in the same package. The need for matching and minimal data skew requires that the parts of an analog subsystem be in the same package. The challenge is in managing the differences between the processes for ADCs and DACs, which are optimized for disparate parameters.
>COMMUNICATIONS CIRCUITS need high-linearity and low-distortion specifications. The move to digital modulation adds very high requirements for linearity, settling time, and distortion in a digital transmitter. The challenge is to improve speed and linearity while simultaneously reducing power consumption.
>PACKAGE SIZE continues to decrease, from surface-mount packages, to SOT, and even to chip-scale packages, which are really just encapsulated dies with a set of external connections. The smaller packages allow for minimal footprint and also simplify signal routing on the pc board.
>DATA CONVERTERS FOR IF APPLICATIONS are coming online. The zero-IF transmitters are still a few years away, so intermediate architectures are going to prevail for a while. These parts must have a large dynamic range and low noise and distortion to minimize the processing load at the DSP, allowing the DSP to perform all demodulation.
>EXPECT MORE DACs IN SOI (silicon on insulator) as frequencies go up to 1.8 GHz to also meet the requirements for low noise. The existing silicon processes are not able to meet all of the device specifications for speed and noise. The costs of the exotic processes, however, may become a hurdle, as the higher-performance parts cannot maintain too much of a premium over the lower-performance parts.
>THE TREND TO SMALLER PROCESS GEOMETRIES in the digital sections of the systems forces lower supply voltages. The converters will have to track the rest of the system, or it will necessitate adding level translation functions on the digital inputs. The overall system compatibility is an issue if the system designers are going to get their money's worth from the high-bit-count converters without having to add more parts just to interface the low-voltage digital logic to the high-voltage analog.
>INTELLIGENT CONVERTERS will take advantage of the logic process scaling to add functions that will provide local data processing before transferring the data to the outputs. The converters will become more power-aware. They will use the local built-in intelligence to limit power consumption to only those intervals that require operations.
>REDUCTION IN PERIPHERAL COMPONENTS: The inclusion of local intelligence in conjunction with the increases in integration levels means that more converters will have self-calibration and linearity and offset compensation on-chip. This signals the early ending of the "binary" voltage references and tighter closed-loop control of the external transducers without much intervention from the digital controllers.