Electronic Design

ASIC Verification Software Automates Partitioning

Productivity for ASIC designers is a hot topic these days. In particular, FPGA-based prototyping flow can be a huge bottleneck. But new technology is available that enables designers to automate many of the tasks related to ASIC prototyping, including partitioning, gated-clock conversion, and pin multiplexing. This can save designers days or even weeks in the prototyping process.

In version 5.0 of its Certify verification synthesis software, Synplicity Inc. of Sunnyvale, Calif., allows users to automatically partition an ASIC design onto multi-FPGA custom boards for prototype development (see the figure). The tool also offers enhancements to existing automatic gated-clock conversion and pin-multiplexing features to increase the speed and performance of ASIC prototypes.

Previous versions of Certify offered what Synplicity called guided interactive partitioning. Although the tool gave users a good deal of feedback in terms of I/O and area usage, partitioning was still performed manually. Version 5.0 takes the partitioning technology to the next level of fully automatic partitioning.

Earlier attempts at automatic partitioning were made at the gate level, a method that's more difficult to pull off successfully. Implementation has already been chosen at that point, resulting in either performance or area compromises. Partitioning at the register-transfer level eliminates those compromises and affords much more flexibility.

Certify 5.0 employs an extremely sophisticated algorithm that takes into account both I/O usage and area usage. It's also very fast. One Sun SPARC design of about 600 kgates was partitioned on a Pentium III machine in 44 seconds. Larger designs of up to 2 million gates can take anywhere from two to 10 minutes, depending on complexity and board configuration (how many FPGAs, how large they are, how many I/Os, and so on).

Users don't sacrifice manual partitioning capability. In fact, they can manually partition the segments of their design that are most critical in terms of performance, and then direct the tool to automatically partition the rest of the circuit. Or, they can run a fully automatic partition, examine the results (the tool retains the extensive feedback features of older Certify versions), and then tweak the partition to achieve their goals.

According to product marketing manager Brian Caslis, the tool's automatic partitioning results are about as good as those achieved by an experienced ASIC prototyper. "In the cases of a few designs that we tested, a good designer wasn't able to achieve a partition after a couple of days of effort, while the tool could," he says.

Earlier versions of Certify incorporated the ability to recognize gated clock-tree structures in an ASIC and convert them to clock enables in an FPGA. In addition to the logic gate elements previously recognized in the clock tree, the tool can now detect clock trees with inferred and instantiated memories and latches, instantiated registers, shift registers, state machines, and counters. This eliminates the time-consuming task of manually converting gated-clock elements.

The tool's pin-multiplexing capabilities have also been enhanced to provide users with the flexibility to choose more multiplexing implementations. It enables designers to time-divide signals between pins and share I/Os on a device to conserve pins.

Version 5.0 of Certify costs $115,000 for Windows NT, Windows 2000, and Unix. Current customers will be upgraded at no charge. For more information, visit www.synplicity.com.

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