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Electronic Design

Background Debug Mode Speeds Up 16-Bit Microcontroller Application Development

Built-in hardware debugging lowers software development costs and speeds delivery of applications.

Microcontroller designers typically strip down the hardware to the bare minimum. This generally requires an expensive in-circuit emulator (ICE) to debug applications. Now, Motorola has found a way around this.

Its new HCS12 line of 16-bit microcontrollers includes a built-in background debug mode (BDM) that eliminates the need for an ICE. This significantly lowers development costs and makes microcontroller development practical for smaller shops. BDM also allows in-circuit debugging, making field diagnostics practical.

The architecture is similar to that found on higher-end 32-bit microcontrollers. A small pod connects the microcontroller to a PC. It handles protocol conversion from the single-pin microcontroller BDM interface to the serial PC interface.

The HCS12 is made on a 0.25-µm process and supports a bus speed of 25 MHz. It uses 2.5 V for internal logic and has a voltage regulator that handles 2.5 to 5 V. I/O ports can operate at 5 V. Various specialized interfaces are supported, including CAN, I2C, SPI, and SCI/serial buses.

Numerous other new features are incorporated in this product line to provide faster execution and improved memory handling (see "New HCS12 Features," p. 45). But the key feature is the BDM.

Among other modules, the HCS12 contains a BDM module. It has an independent state machine to handle the single-line interface (Fig. 1). Therefore, the BDM module can operate asynchronously with the rest of the HCS12 system and access on-board memory without stopping the processor. Microcontrollers with a JTAG debugging architecture must halt the processor to access on-board memory. This must be done for all operations, such as setting breakpoints, reading memory, or changing the contents of memory. In many cases, stopping the processor during a test can render the test useless. For example, incoming data may be lost when a JTAG-enabled processor is stopped. While BDM does not completely eliminate the need to halt the processor while debugging, BDM does minimize the problem.

Cycle Stealing Minimizes Interference: The BDM memory access support is designed to minimize interference with the system using cycle stealing. It waits up to 128 cycles for an unused memory access slot to perform its operation. If the BDM module can't steal a cycle during this time, the processor will have to wait one cycle while the BDM module completes its operation. Because the BDM interface runs over a comparatively slow single pin, and eventually a serial-port interface, the BDM module delays the processor only a minimal number of times.

A pair of hardware breakpoint registers in the BDM module can be programmed for independent operation, tracking program, or data addresses. These registers can also be combined into a single, complex breakpoint that's triggered when a particular instruction and data combination occurs.

The hardware breakpoint support provides a single-instruction trace capability. This is tied into an on-chip debugger program located in a protected area of flash memory. The on-chip debugger program also supports software breakpoints using flash patching. This enables setting more program breakpoints than the two hardware breakpoints.

But flash patching is less efficient than hardware breakpoints. For example, flash patching is only applicable to program breakpoints. It can cause an interrupt each time the code is executed, and the original instruction must be restored before the debugger can single-step through the interrupt.

The other disadvantage of software breakpoints is that they can only be set when the application code isn't running. Hardware breakpoints can be changed while the application code is running.

In addition to accessing memory and configuring breakpoints, the BDM module can interrupt the processor when requested by the debugging program running on the PC. This is essentially the same as a nonmaskable interrupt. The interrupt saves the processor state and enters the on-chip debugger.

Faster Execution: The HCS12 family of processors has a register architecture that's essentially identical to Motorola's early 16-bit microcontrollers, providing a clear upgrade path (Fig. 2). New instructions and indexing modes provide more efficient execution, reduced code size, and improved performance.

A 1-byte loop instruction works with a 1-byte postfix and provides 72 variations on comparisons, register usage, and auto decrementing/incrementing. Another such instruction provides a very general transfer/exchange instruction that can operate with different size operands using sign-extend or zero-extend operations. These transfer operations also support pre- and post-auto decrementing/incrementing with offsets between 1 and 8 bytes. The offsets are ideal for stepping through tables of small structures frequently found in embedded applications.

Memory access instructions support 5-, 9-, and 16-bit offsets. Seven of the indexing modes are new to the HCS12. The smaller 5-bit offsets are great for accessing local variables and reducing the instruction size, compared to the larger offsets. The smaller offsets work well with high-level language code from C and C++ compilers. All indexing registers can be used with these offsets.

The HCS12 also includes fuzzy math and logic instructions. These are handy for implementing fuzzy math algorithms without resorting to higher-performance processors.

The processor architecture includes a 3-word instruction queue. Although not as sophisticated as a large cache, it provides 1-cycle execution for most instructions.

Memory Improvements: Both flash memory and EEPROM are included in the HCS12. EEPROM is important in automotive applications, where the HCS12 is often found.

Program memory is stored in 64-kbyte flash memory modules. The product line supports up to four modules for a total of 256 kbytes of program memory. Each module can be programmed independently, so one block can be erased while another is programmed. This speeds up the installation of software updates.

The chip supports byte-level programming, and 16 bits can be programming in 20 µs. A burst-programming mode allows a range of bytes to be programmed more quickly than programming bytes individually. It takes less than five seconds to program 128 kbytes of flash memory.

Each block supports up to two protected areas that may start at the bottom or top of the memory block. Protected areas can't be programmed until the protection is removed. Motorola has added timing-logic and state-machine support for programming the flash memory, so updates no longer depend on software timing algorithms.

On-chip RAM has been optimized as well. There's no access penalty for misaligned word accesses. These word transfers occur in only one cycle, as do aligned transfers. Bit, byte, word, and limited nibble access is supported.

The HCS12 product line supports a range of memory configurations and a range of peripherals. Its general-purpose I/O tolerates multiple keyboard interrupts, letting the processor wake up from the standby mode.

Other peripheral support includes high-performance 16-bit timers, 8- and 10-bit analog-to-digital converters, four-channel pulse-width modulation (PWM), serial interfaces, controller-area-network (CAN) interfaces, and SAE J1850 Class-B Byte Data Link Control (BDLC) interfaces. BDLC and CAN interfaces are often used in automotive applications.

Development Tools: The HCS12 Development Kit includes an HCS12 Evaluation Board (EVB) and the Serial Debug Interface (SDI), along with the MCUez Development Toolset. A number of EVBs are available for different microcontrollers in the HCS12 family. The EVBs feature a prototype area for custom logic.

The SDI provides access to the on-chip BDM from the MCUez debugger (Fig. 3). The MCUez tool suite also includes a Windows-based linker, assembler, and C compiler.

Price & Availability
Processor pricing depends on the built-in peripherals and the amount of flash memory and RAM. A range of devices is available immediately. The 256k flash-equipped MC9S12A256BC is priced at $11.88 each, while the Development System Kit costs $495.

Motorola Semiconductor Inc., 6501 William Cannon Dr., Austin, TX 78735-8598; (954) 267-5000;

New HCS12 Features
Dual hardware breakpoint registers
  • Single-pin interface
  • Protected debug memory
  • Memory access uses cycle stealing

  • Faster execution
  • New, compact instructions
  • Indexing employs 5-, 9-, and 16- bit offsets
  • Most instructions are single-byte
  • Three-word instruction queue

  • Flash memory
  • Fast write and burst programming modes
  • Program-mode timing handled by hardware
  • Two block-protection areas per 64-kbyte module

  • RAM access enhancements
  • Single-cycle RAM access
  • Includes misaligned word accesses

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