Moving a design from board to chip is easier with a multithreaded nonblocking interconnect. That's exactly the on-chip interconnect approach taken by Sonics. Its SiliconBackplane III is designed to work with any core that utilizes the Open Core Protocol (OCP) interface. An OCP master is mated to a SiliconBackplane master agent. Part of the agent is customized for the respective core. The other part is a standard SiliconBackplane component that interfaces to the low-latency, 4-Gbyte/s switched interconnect using a request/response protocol.
New burst agents merge multiple requests into one packet for more efficient use of the interconnect. Another agent handles 2D image transfers, where data isn't always at sequential addresses.
A single-use license costs $240,000, plus a royalty per chip.
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