Solving and managing heat-related problems are crucial to the success of 3D packaging technology. These challenges intensify as chip performance and density increase, and as the clamor for smaller form factors and lower costs reaches a fever pitch.
Making some noise on this front is the Georgia Institute of Technology, with a potential solution that could bring great dividends to 3D package cooling. A liquid-cooling technique developed by researchers Paul Kohl, James Meindl, Bing Dang, Paul Joseph, Muhannad Bakir, and Todd Spencer uses microfluidic channels that can be integrated onto the backs of IC chips. On top of that, their technique can be made on a CMOS-compatible process. The wafer-level fabrication technique includes polymer pipes that will allow electronic and cooling interconnections to be made simultaneously via automated manufacturing processes.
“This scheme offers a simple and compact solution to transfer cooling liquid directly into a gigascale chip, and is fully compatible with conventional flip-chip packaging,” says Dang. “By integrating the cooling microchannels directly onto the chip, we eliminate many of the thermal interface issues that are of great concern.”
To date, nearly all chip cooling techniques—commercially available techniques as well as those under development in the lab—employ cooling liquids in modules attached to a chip or in microchannels fabricated and bonded on the back of a chip. These approaches have limited heat-transfer capabilities and operate at chip-damaging bonding temperatures of 400° to 700°C. The Georgia Tech technique works at only 260°C, making it compatible with CMOS processes.
The technique begins by etching 100-mm deep trenches on the back of a silicon wafer (see the figure). Next, a layer of high-viscosity sacrificial polymer is spin-coated on the back of the chip to fill the trenches, followed by a polishing step that removes excess polymer. Then the trenches are covered by a porous overcoat, and the chip is gradually heated in a nitrogen environment. Heating causes the sacrificial polymer in the trenches to decompose and leave the channels through the porous overcoat, leaving microfluidic channels behind. Another porous overcoat is applied over the microchannels to make for a watertight system.
The researchers also built through-chip holes and polymer pipes that allow the on-chip cooling system to connect to embedded fluidic channels built into a printed wiring board. They’ve already demonstrated that the on-chip microfluidic channels can be joined at the same time that the IC is connected electronically, using conventional flip-chip bonding. The microchannels withstand more than 35 lb /in. 2 of pressure. Calculations have shown that the system should cool to 100 W/ cm 2.The work is being sponsored by the Microelectronics Advanced Research Corp. (MARCO) and the Defense Advanced Research Projects Agency (DARPA).