As portables, like notebook computers, PDAs, and barcode readers get slimmer, lighter, and sexier, the demands on the power electronics continue to rise. Along with the numerous low-voltage supply rails have come brutal, zero-to-maximum-CPU-load transients that characterize power-minimizing, clock-throttling techniques. All this is coming at a time when the shrinking size of notebooks makes waste-heat dissipation a serious problem for system, thermal, and mechanical designers.
For the moment, the classic solution—the standard buck topology—remains the design of choice. Armed with the latest MOSFETs and inductors from the desktop world, the buck topology can tame the waste-heat problem as well as any esoteric configuration. In addition, new controllers, tailored to the demanding CPU loads, allow the hot dc-dc circuit to be placed at least somewhat distant from the already-hot CPU. However, designers can employ a number of additional techniques to mitigate these electrical and thermal problems. Although the techniques used for managing future power needs currently apply to notebook computers, soon they will be used with a broader range of portable and handheld equipment.
Upcoming Power Needs As chipset supply voltages migrate downward, the main power distribution rails in a typical notebook are shifting from 5/3.3 V down to 2.5/1.8 V. These lower voltages, which don't exist in today's systems, power RAMbus, RDRAM, and chipset rails, are scheduled to appear in notebook systems in 1999.Regardless of what the CPU supplies do, motherboard supplies are becoming more complicated as new voltages are introduced, without getting rid of old power-supply rails first. For example, the move from 3.3 V to 2.5 V for DRAM won't eliminate 3.3 V for a long, long time, due to the legacy of 3.3-V Cardbus cards. At some point, the 12-V rail might disappear, but even that won't happen soon.
Along with dropping voltages, the complexity of notebook power supplies has been evolving at a tremendous rate. Six years ago, we were seeing only one supply rail (5 V), sometimes obtained by powering the entire system directly off a naked stack of four NiCd cells. In 1999, there will be at least seven rails (12, 5, 3.3, 2.5, and 1.8 V, plus VI/O, and VCORE). Amazing!
Topology Choices As more supply rails appear, our job as power-supply designers is to make each dc-dc converter physically smaller while generating less heat. Accomplishing this mandates a complete reexamination of the fundamental power-supply design, products available, and specific tricks and trade-offs used—particularly for the demanding CPU core supply.Choosing the right switching topology can be vexing. There are a surprising number of choices, each with merits and drawbacks. Sadly, many of the niftier choices from past designs are unusable today. For example, linear regulators, desirable due to their fast transient response, are now forbidden because their efficiency (equal to VOUT/VIN to a first order) has gone downhill as voltages have dropped. At sub-2-V levels, even the most minimal 200 to 300 mV of headroom needed for adequate transient response makes the waste-heat picture bleak. So, linear regulators are out, even when used as post-regulators to improve the transient response of switch-mode supplies.
Coupled-inductor buck regulators, which stack a flyback winding on top of the main buck output to generate a second output almost for free, are tempting as an easy way to make VCORE and VI/O simultaneously. However, the exact value of VCORE is a fast-moving target (a colleague jokingly calls it "voltage du jour"), which could force a painful transformer re-design with every processor upgrade. Most other multiple-output schemes must be rejected for this reason, or due to low efficiency or poor cross-regulation.
Some topology candidates do make it through the initial weeding-out process (see the table). Efficiency is listed two separate ways because of the importance of the impact worst-case waste-heat generation has on thermal design.
Three-Terminal Devices The three-terminal autotransformer buck topology is interesting because it can be employed to adjust the duty factor by changing the turns ratio. This eases the power-dissipation burden on the synchronous (low-side) switch, which otherwise sees greater than 90% duty. Equalizing the duty between high- and low-side switches also helps when designing the pulse-width-modulation (PWM) control loop, because extremely short control-switch on-times are avoided. However, the switch-stress voltage and switching losses are increased—and you have to add an extra termination to the inductor (an expensive redesign when the total series resistance needed for good efficiency is less than 4 mΩ).High-Frequency Converters The classic forward converter also is nice, because it deals effectively with high input/output-voltage ratios, and can be made small enough to be placed close to the CPU. But the need for a transformer, and the extra complexity of two magnetic components, makes the forward topology unattractive.
On the surface, resonant-mode topologies look promising due to small component sizes. However, under the microscope, these topologies all show some fatal flaw when placed in the demanding notebook environment. For example, the zero-current-switching (ZCS), parallel-resonant buck converter has high peak currents (bad for efficiency due to I2R losses) and hideous output ripple, while the zero-voltage-switching (ZVS), quasi-resonant buck has high switch-stress voltage; needs a back-to-back, reverse-blocking MOSFET; and has problems dealing with wide load-current variations.
While the resonant schemes do provide very small size, all of the schemes examined have penalties in terms of efficiency and waste heat when compared to conventional buck regulators. Why make a tiny dc-dc converter that you can place close to the CPU (for good transient response), when it can overheat your already-hot CPU?
Buck Converters Two-stage buck regulators, where a miniature, fast dc-dc converter is powered from the system 5-V supply rather than the battery, will win out in some designs. Small, local converters can be placed very close to the CPU, where they can rely on the existing bank of ceramic bypass capacitors for output filtering. This raises the partitioning issue of where to place the CPU VCORE dc-dc converter.For manufacturing ease, modern notebook CPUs are usually placed on daughtercards or inside modules. If the converter is on the motherboard, there are a lot of parasitic resistances and inductances from the pc-board traces and connectors to play havoc with the load transient response. A massive "capacitor farm" may be needed to cope with pc-board impedances. On the other hand, if the dc-dc converter is on the daughtercard, it adds waste heat in exactly the worst possible area.
The standard one-stage buck regulator powered directly from the battery still appears to be the overall winner, depending, of course, on your design priorities. The basic buck regulator is elegant, simple, and extremely tough to beat. Its worst flaw is the size of the inductor, which tends to push the converter away from the CPU (which, maybe, isn't such a bad thing, again, because of heat). However, we can hone the basic buck regulator to a sharper edge using the latest MOSFETs, inductors, and control ICs.
Designing For Mobile CPUs Upcoming Mobile Pentium II modules act a lot like desktop Pentium II modules from a power-supply perspective. They draw a lot of current (7 A) in sharp load steps and need good dc precision at about 1.5 V. One version has voltage-identification codes (called "VID codes" in the desktop world) present on connector pins to set the power-supply voltage. The worst-case continuous current draw for thermal calculations is about 5.5 A, which helps with capacitor ripple-current ratings and MOSFET package-power dissipation.The VCORE dc-dc converter shown here features 90% efficiency (Fig. 1). An integral digital-to-analog converter (DAC) sets the output voltage between 1 and 2 V in 50-mV steps. Note that the 4-bit DAC codes (VID codes) for notebook CPUs are completely different from the 5-bit codes used in desktop computers.
The MAX1710, which is typical of the many fast, high-precision dc-dc controllers available today, has several innovations that designers should look for in VCORE applications. The device requires no current-sense resistor, which gains the circuit at least 4% increased efficiency at any load level. It has brawny MOSFET gate drivers that force the FETs quickly through the transition region to ensure low ac losses. The 3-A pull-down device in the low-side gate driver is especially beefy. This prevents parasitic capacitive coupling (due to the gate-drain charge of the monster synchronous switch) from yanking up on the gate when its supposed to be held low. This can potentially cause noisy, efficiency-killing, shoot-through currents.
Two-Wire Remote Sensing Two key circuit blocks allow this battery-powered converter to be located remote from the CPU, while providing nearly the same transient response as a two-stage local converter operating at 1 MHz. First, dc voltage drops in the ground, and power buses are dealt with by an uncommon, two-wire remote sensing scheme. This scheme requires a total of four pins on the controller: the fast feedback and ground (FB and GND) pins regulate large dynamic changes seen at the converter, while the slow feedback and ground-sense (FBS and GNDS) pins regulate the remote dc voltage at the CPU.The integrated remote-sense signal is summed into the fast feedback loop with just enough gain to correct for 25 mV of ground or power-bus drops. Some chips have separate power and analog ground pins (PGND and AGND), but really need to have both these pins connected to the ground plane close to the IC. This new class of chip has three ground pins—PGND, AGND, and GNDS—allowing the GNDS trace to be snaked around the pc board to the remote load while keeping the analog section of the IC quiet (by connecting AGND close to the IC).
Making A "Fast Buck" Once the dc drops are dealt with, the next problem is pc-board trace resistance and inductance. The solution here, as in most situations, is to put a large portion of the required bulk capacitance fairly close to the CPU. To make this work in practice, your dc-dc controller must have a fast transient response and a stable feedback loop. It must have this stability in the presence of fairly high values of capacitor-series resistance caused by the added pc-board resistance.The instant-on nature of the constant-on-time PWM gives this circuit a fast response. When a nasty load step comes along and causes the output voltage to sag, the PWM turns on the high-side MOSFET within 100 ns of the load step, and dumps massive amounts of current into the load. This admittedly whacks the battery supply pretty hard, but the surge-current problem is much easier to deal with at 15 V than down at 1.5 V. This is a result of the less-stringent voltage tolerances and greater energy-storage capability of capacitors up at the battery voltage level.
The VCORE converter is designed for a wide range of input voltages. The circuit here accepts inputs from 7 to 22 V, which accommodates the entire input-voltage spectrum—from a discharged, three-cell, lithium-ion battery to the maximum ac adapter voltage seen in four-cell systems when the battery has been removed.
There's a 5-V power input as well as a battery input, so that gate-drive power can be derived from the highly-efficient system 5-V supply, rather than inefficiently from the battery by way of a linear regulator. The lack of this particular feature (a 5-V linear regulator for chip biasing and standalone capability) indicates how specialized dc-dc controller chips have gotten, to the extent that a complex, feature-laden, 24-pin device must have another IC generate the chip bias power.
Newer Inductors And MOSFETs As usual, the maximum input voltage and the switching frequency dictate the inductor size. Frequencies in the range of 200 to 400 kHz are the sweet spot for use with today's MOSFETs. Operating moderately deep in the continuous-conduction region, with 30% inductor ripple, provides a good compromise between efficiency and transient response. These design decisions dictate a 2-µH, 10-A inductor. Fortunately, the cutthroat, high-volume desktop market has created some excellent low-cost surface-mount inductors from companies such as Coilcraft, Coiltronics, Panasonic, and Sumida, among others. For this design, a 2.2-µH, ferrite E-core design having flat wire is chosen, thanks to a winning combination of small size and low dc resistance.There's a small, but vicious struggle occurring between the three leading-edge notebook MOSFET manufacturers—namely Fairchild, South Portland, Maine; International Rectifier, Segundo, Calif.; and Vishay-Siliconix (formerly Temic), Santa Clara, Calif. Each wants to dominate the expanding market for dc-dc-optimized, 30-V, SO-8 MOSFETs. Each company also tries hard to improve switching speeds by reducing gate charge while simultaneously reducing RDS(ON) to sub-5-mΩ levels. International Rectifier is winning at this time, but before shipping a new design, you should call each company for samples of their latest devices to evaluate your prototype board's efficiency.
Shown in Figure 2, this efficiency graph was made with the 7-A notebook CPU circuit using an IRF7807 high-speed MOSFET optimized for PWM use. The low-side MOSFET was an experimental device, not available to the public at the time of writing, but it will probably be out by the time you read this. Note the dramatic drop-off in efficiency as the output voltage is reduced from 2 to 1 V.
Output-Voltage Error Budget In many cases, the published specs for CPU dc voltage tolerances, transients, and ripple voltages set requirements on each of the ac and dc accuracy parameters. In particular, the allowed ripple, dc error, and transient response are often specified separately. However, the real need, based on numerous discussions with CPU architects and process design engineers, is to maintain the voltage at the CPU pins within a specified window. The power-supply designer should feel free to make whatever design decisions that result in the best overall converter, allocating the error budget as needed between ac and dc errors.
For example, take a hypothetical CPU whose datasheet specifies 1.5 V ±2% dc error, plus 1% peak-to-peak ripple and 2% transient load regulation. What this spec is really saying is that there's a ±4.5% window around 1.5 V. The dc-dc designer should meet this ±4.5% window without regard to the ±2% dc accuracy spec. A tighter dc accuracy in the controller IC, for example, allows for greater noise and ripple, a fact that can be taken advantage of by reducing the size and cost of the output filter capacitors.
Staying In The Window In addition to budgeting the error sources to meet their own priorities, savvy designers will read between the lines of the spec, and violate it selectively where and when it makes sense to do so (at this moment the author offers up a prayer to the great CPU god that he will not strike the author down for his insolence). For example, it's usually not necessary to maintain ±2% dc accuracy when the load is less than one-quarter of the full load. Instead, it's allowable (and actually desirable for better transient response) to let the output float, perhaps 1% high, when in light-load, pulse-skipping mode.The upper limit of the voltage window is determined by the thermal limitations of the CPU. The CPU manufacturers will also say that you shouldn't exceed this value because that's the point where the CPU is tested. Realistically, however, allowing the voltage to float 1% high under light loads isn't going to hurt anything. Similarly, a momentary 1% overshoot when going from heavy to light load isn't going to be a problem. The upper limit of the voltage window is really determined by thermal issues, not transients.
In contrast, the lower limit to the voltage window is a much more sacred barrier. If the voltage ever dips below the magic line, even for a microsecond, data may be corrupted, and the computer may lock up. So, don't push your luck on the lower limit. Improve the transient response of your converter by reducing the inductor value until all the bad effects of high inductor ripple become a headache, back off a little, then pile on the local bypass capacitors to finish the job of staying within the window.