The relentless pace of change in electronics design means an increasing number of challenges for product designers, along with shorter development cycles and tighter budgets. One involves a general trend in the electronics industry away from parallel bus-based interconnections, such as PCI and EIDE, toward high-speed serial interconnects, like Ethernet as a backplane fabric, PCI Express, SATA, RapidIO, InfiniBand, and Star Fabric. These fabrics offer better fault resilience and high bandwidths, but they also have drawbacks.
The high-speed SERDES interconnect, for example, needs careful routing to meet signal-integrity and impedance constraints, especially where connectors are concerned. It becomes increasingly tricky to validate designs when you can no longer see what is happening using an oscilloscope. And the days of the older multichannel parallel logic analyzer are numbered. Now, analyzers must be "protocol aware" so they can drill down into the serial waveform and show the logical transactions present. The abundance of serial interconnect fabrics results in the need for many different analyzers of increasing cost and complexity. So to cut costs, companies often lease, rather than buy, test equipment for the duration of a project. This means that engineers face the stressful task of repeatedly learning to use unfamiliar equipment quickly.
Also, many new devices use high-density BGA packaging, allowing higher pin counts, greater component density, and better signal integrity, but also leading to inaccessible nets on the pc board. High-speed signals often rule out the use of analyzer headers because the electrical stubs can greatly distort the waveform. JTAG boundary-scan cells are included on lower-speed pins or in devices that are less cost-critical, but these only permit interconnection test for production verification rather than high-speed integrity and crosstalk analysis. Prototype board rework is also more difficult.
Lifting a component leg and soldering on a green mod-wire isn't an option with BGAs, so it is vital that engineers perform system-level simulation before manufacture to prevent mistakes resulting in scrap boards and costly re-spins.
Additionally, smaller device geometries mean lower core voltages. Devices often have a core supply and one or more I/O supplies, so complex boards may require four or five voltages. Not only must engineers carefully control the sequencing of these supplies during normal power cycles, they must also consider controlled shutdown under fault conditions to prevent silicon latch-up and component stress.
Moreover, reduced supply voltages require higher supply currents. The 5% tolerance required by most devices corresponds to a lower overall number of millivolts margin. However, Ohm's law still applies, so power distribution becomes more significant. Careful decoupling with low-ESR capacitors is crucial to meet the power-plane noise budget. To overcome many of these issues, designs have tended toward point-of-load regulation, where a higher intermediate voltage is distributed to small dc-dc converters nearby the components where the power is needed. This allows tighter control over the regulation of these supply rails.
The choice of components used in a design is also increasingly important to reducing the engineering support required over a product's lifecycle. For example, using a single-sourced component might be appropriate, but engineers must balance the benefits against the risk of potential obsolescence or long delivery times.
Recent EU legislation such as the WEEE and RoHS directives are also causing turmoil, as different suppliers take different approaches to compliance. There isn't even consistency in how components are marked nor any number to indicate compliance.
The spiraling complexity and density of modern electronic systems present engineers with a uniquely challenging future. Some headaches will ease over time. For instance, new EU directives will become less troublesome once deadlines pass and design practices are better understood. However, the demand for new and diverse technologies will only increase over time. Who knows what sort of test equipment will be required to develop around innovations such as buried passives, optical backplanes, or even organic memories? Fasten your seat belts, because it could be a bumpy ride.