EE Product News

Chip Connects HyperTransport Bus To PCI Devices

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An industry first is claimed for the AP1011, a HyperTransport-to-PCI bridge chip that connects the HyperTransport bus, formerly known as the lightning data transport (LDT), on microprocessors, network processors, and ASICs to a wide variety of PCI devices and peripherals. This new bus is designed to move data from processors to peripherals at speeds up to 60 times faster than a 32-bit PCI bus operating at 66 MHz. Connection to the bus from the chip is configured with an eight-bit data path clocked at both edges at 533 MHz for a 1 GB/s transfer rate.
The chip integrates transceivers and buffers to directly drive four 33-MHz PCI slots (or two 66-MHz slots), or more loads if connected to PCI chips on the motherboard. And it can drive 32- or 64-bit PCI buses as well as its own HyperTransport connections.
Other features include selectable bus speeds of 25, 33, 50 and 66 MHz, 55 pins that run downstream from the processor, and a forwarded path for all HyperTransport packets that do not match its address space. The AP1011 is sampling now with production quantities scheduled for June 2001. Packaged in a 352-pin SBGA, price is $95 each/1,000.

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