Electronic Design

Clock Distribution Devices Handle Flexible Design Choices

The first member of the ispClock5300S family of in-system programmable, zero-delay, single-ended universal buffer devices is the 12-output ispClock5312S. The devices offer programmable clock skew, termination, and interface standard support. They accommodate four operating configurations: zero-delay buffer mode, combined zero-delay and non-zero-delay fan-out mode, dual fan-out buffer mode, and fan-out buffer with output dividers.

The ispClock5300S devices use three 5-bit on-chip output counters to generate up to three clocking frequencies up to 267 MHz derived from one reference. The universal fan-out buffer has a maximum pin-to-pin skew of 100 ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70 ps and the period jitter is less than 12 ps (rms). The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length. Also, the universal fan-out buffers support a range of single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of output voltages, while reference inputs support single-ended or differential inputs. The ispClock5312S comes in a 48-pin TQFP in both commercial (0 to +70 deg. C) and industrial (-40 to +85 deg. C) grades.

The ispClock5312S is available immediately. The ispClock5308 (eight outputs) and ispClock5394 (fout outputs) are scheduled to be introduced in the second half of 2006.

The ispClock5312S starts at $3.00 in 10,000-unit quantities.

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