Electronic Design

Clock Synthesizer Optimizes Timing Performance

The CDC7005 low-phase-noise clock synthesizer reduces board space by 70% by combining multiplying, dividing, and jitter cleaning features. Ultimately, this gives board designers the advantage of optimized timing performance. Also integrated are a low-noise phase frequency detector, precision charge pump, programmable dividers, an operational amplifier, and a 1:5 differential clock buffer with dividing options. As a result, the compact chip cuts board costs and the amount of discrete components. It synchronizes a voltage-controlled crystal oscillator, or VCXO (10 to 800 MHz required), with a reference clock. The CDC7005 accepts a 3.5- to 180-MHz reference clock. Five low-skew, differential outputs are standard. Packaged in a small and thermal optimized 64-pin BGA, the CDC7005 suits communication, instrumentation, and industrial applications. Its low phase noise performance benefits many signal chain devices, including analog-to-digital converters, digital-to-analog converters, serializers, ASICs, and DSPs requiring precise reference clocking. The CDC7005 clock synchronizer costs $13.80 each in 1000-unit lots.

Texas Instruments Inc.
www.ti.com; (800) 477-8924, ext. 4500

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.