To quickly develop a new generation of ultra-high-density voice-processing systems, Spectrum Signal Processing of Burnaby, Canada, has formed a technology and marketing alliance with telecom giant Broadcom Corp. Spectrum will use Broadcom's BCM1500 advanced multicore RISC/DSP processor—also known as Calisto for configurable algorithm-adaptive instruction-set topology—to develop voice-processing boards for use in communications gateways.
Spectrum is readying next-generation voice-processing boards with a tenfold improvement over previous DSP-based technology. "Using Calisto and our proprietary processing chips, we are developing board-level solutions using industry-standard buses like PMC and CompactPCI," says Tim Botham, Spectrum's director of marketing for network solutions. The boards will be available in the third quarter.
There are two main thrusts in this initiative: flexibility and ultra-high density. Consequently, Botham notes, the boards will let developers target a variety of voice-processing gateways. The industry now offers between 240 and 500 channels on a PCI Mezzanine Card. "We expect to leapfrog such den-sities with our Calisto-based solution," he says.
Spectrum is using C54x DSPs in its aXs family of packet voice-processing boards. The Calisto-based boards are a totally new design. They employ modular algorithms and embedded packet telephony software developed at Broadcom. The packet telephony software resources were brought on board with Broadcom's acquisition of HotHaus Technologies last year. Some of these algorithms include voice compression, echo cancellation, tone detection and generation, IP packetization, ATM cellification, and delay equalization.
The communication gateways these boards will serve are deployed in the telecommunication infrastructure. They let voice, fax, and data traffic pass between two different networks, such as traditional circuit-switched telephone networks and packet-based networks, including the Internet.
Broadcom has taken the Calisto communications processor to production using a 0.18-µm CMOS process. The company is now migrating to 0.13-µm CMOS to slash power consumption in half. Typical power consumption is 2 W. Doubling the clock frequency is on the horizon, too.
Calisto, which boasts 2.7 billion instructions per second of DSP horsepower and 830 RISC MIPS, was added to Broadcom's monolithic communications processor arsenal when the company bought Silicon Spice last year. The device combines 16 166-MHz DSPs and five RISC processors on-chip. Each DSP core in the 4-by-4 Spice array uniquely combines scalar and vector processing, says Nadav Ben-Efraim, product-line manager for Broadcom's carrier access business unit.
They aren't traditional DSP cores. "Like other processors, Calisto is not a black box solution," Ben-Efraim notes. "While we provide our own software to run on Calisto, it has room to add user software."
Some key features include on-chip SRAM with a 26-Gbyte/s transfer rate, 664-Mbyte/s off-chip DRAM speed, two 50-Mbit/s Spice Bus channels, an Intel/Motorola host port interface for controlling additional devices on board, DMA for memory test/repair, and boundary scan/JTAG test support (see the figure). An IDE that supports the processor includes an optimizing C compiler, a signal-processing framework or real-time operating system, and applications software.
For more information, visit www.spectrumsignal.com/network_solutions.