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Electronic Design

Custom Linear Array Incorporates Up To 48 Precision Op Amps Per Chip

Leveraging its patented electrically programmable analog devices (EPADs), Advanced Linear De-vices has crafted a custom linear circuit array that comprises up to 48 precision op amps on a single CMOS chip. In essence, this high-density op-amp ASIC can electrically trim each amplifier within the array to better than 1.0 mV for high-precision applications.

Yet this ASIC design methodology isn't limited to op amps, says John Skurla, marketing director at ALD. Other functions like comparators, analog switches, and data converters can be implemented as well. Although the op amps and other functions are restricted to ALD's EPAD-based devices, the specifications can be tweaked if necessary to meet the designer's needs, Skurla adds.

Using ALD's new methodology, multiple channels of these precision analog circuits are arrayed or multiplexed onto one linear CMOS ASIC chip. Consequently, each EPAD op amp serves as a precision single-channel building block in this design. Typically, each EPAD device has a voltage injection pin for trimming. With multiple channels, it isn't feasible to bring all the voltage programming pins to the outside world.

"Therefore, with a multiple-channel ASIC, we use an on-chip multiplexer that permits you to direct the injection or programming voltage to the right op amp," Skurla explains. Proprietary analog switches are configured on-chip to attain the desired multiplexer circuitry. "The multiplexer is a key function that makes such a high-density precision op-amp chip feasible," he adds.

For sensor applications, a one-channel analog circuit has been developed. It comprises six op amps, each performing a specific task (see the figure). In this single-channel scheme, one op amp provides gain amplification, another offers system offset adjustment, a third permits sensor compensation, a fourth does summing, a fifth allows level shifting, and a sixth is used as an input buffer. Using its new methodology, up to eight channels can be packed on one CMOS chip. That translates to a maximum of 48 precision op amps per die.

Many real-world applications need hundreds of channels per system. For example, ALD has developed an op-amp array ASIC for a customer designing a system with 512 analog channels. Only 64 such ASIC chips are needed to obtain 512 analog channels (see the figure, again). With this approach, 3072 op amps have been crammed on a miniature board. With conventional methods, trimming thousands of op amps is impractical. Robert Chao, ALD's president, says, "Our EPAD-based linear ASIC design can make such tasks simpler and cost-effective."

Since the custom design is based on predesigned and pre-engineered analog cells, this ASIC methodology is inexpensive. "These analog cells are the backbone of this high-density op-amp ASIC approach," Skurla says. Constructing an ASIC chip involves calling out, laying out, and then arranging these predesigned op-amp cells using in-house engineering skills and tools.

When the design process is complete, a custom mask set is generated and a prototype chip is built. The entire design process takes about four to six months. The NRE costs could be well over $75,000, depending on the number of variables. Packaging, the number of leads per ASIC package, the EPAD op-amp specifications used, and quantity can all influence the chip's cost.

On a per op-amp basis, costs are comparable to discrete op-amp chips. But the real savings are in reduced assembly costs, pc-board size, and number of boards within the system, Skurla says. And if the system has a space constraint, this approach can be cost-effective while enhancing reliability by using fewer IC packages and connections.

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