Electronic Design

David Maliniak’s DesignCon Blog: Day 3

DesignCon 2006, or at least the exhibition portion of it, wound down today with what appeared to be the best-attended day of the conference. The exhibitors I spoke to seemed pleased with their booth traffic, both in terms of quantity and quality. DesignCon turned out to be “the little conference that could.”

From an EDA editor’s perspective, though, it’s curious that while DAC’s big announcements are of the moment, the big news I gathered here is for announcement either later in February or early in March. So while this will be the last of my daily DesignCon updates, there’s more to come from this week spent at the conference.

Today’s meetings were mostly upbeat. GigaScale IC’s president Adam Traidman was crowing about Synopsys’s Professional Services’ decision to adopt GigaScale’s InCyte chip-estimation software for early die-size assessments. Additionally, this week marked the first anniversary of GigaScale’s www.chipestimate.com, where a free version of the software is available for use. According to Traidman, more than 4100 users of the site have run some 22,000 designs through the tool.

Formal-verification vendor Real Intent has announced an OEM agreement with Novas Software. According to marketing director Rich Faris, the agreement gives Real Intent the right to resell Novas’s graphical user interface with its Verix formal engine running under the hood. Tight integration with Novas’s Verdi automated debug environment melds the power of the Verix formal engine with Verdi’s property management and debug capabilities.

Pittsburgh-based (how ‘bout them Steelers?) startup DesignAdvance is showing signs of leaving the nest and standing on its own two feet. DesignAdvance’s flagship tool, CircuitSpace, brings much-needed automation to the manual and tedious process of placing components on PC boards. The company has completed a second $3 million round of funding and has also graduated from The Technology Collaborative’s Jumpstart program. The bad news there is that CEO Randy Eager and his staff loses rent-free office space next to its incubator, Carnegie Mellon University. The good news, though, is that DesignAdvance looks ready to run with what looks like an innovative product.

Speaking of innovation, DesignAdvance’s CircuitSpace got a huge boost from its win of a DesignVision award from the International Engineering Consortium here at DesignCon. CircuitSpace beat out tough competition in the PCB design tools category. For the record, here are the rest of this year’s DesignVision Award winners:

  • ASIC & IC Design Tools:
    Cadence X Architecture Design Solution — Cadence Design Systems

  • Design Verification Tools:
    Pioneer-NTB SystemVerilog Testbench Automation Tool — Synopsys

  • Interconnect Technologies and Components:
    Crossbow — Amphenol TCS

  • Semiconductors and ICs:
    Actel Fusion Programmable System Chip — Actel

  • Semiconductors and ICs (IP):
    1T-SRAM CLASSIC Memory Macros Family — MoSys

  • Structured/Platform ASIC, FPGA, and PLD Design Tools:
    HardCopy II Structured ASIC Design Flow — Altera

  • System-Level Design Tools:
    WEBENCH Active Filter Designer — National Semiconductor

  • Test and Measurement Equipment:
    BERTSCOPE CR Clock Recovery — Synthesys Research

    Let’s hear it for the winners!

    I had a chance to catch up with Nancy Eastman, director of Altium Designer Applied Technologies, which recently launched v6.0 of its Altium Designer unified product-development environment. The latest news is that Altium has added support for discrete processors to the environment, including PowerPC and ARM devices. Designer 6.0 gives designers the flexibility to plug a processor into their designs and worry later about implementation options. Har.dware/software partitioning can be thought of as an optimization step as opposed to a world-defining decision.

    There’s also new support for the Xilinx MicroBlaze FPGA-based soft processor for embedded designs. As a result, developers using Xilinx FPGAs and the Xilinx Embedded Development Kit can take full advantage of the Altium Designer environment to develop MicroBlaze-based systems.

    At a conference that has so much emphasis on high-speed design, it was only fitting to have a chat with Ansoft, a purveyor of tools that have everything to do with high-speed IC and interconnect design. Ansoft’s director of business development, Larry Williams, spent some time explaining the synergies between Ansoft’s HFSS 3D field solver and its Nexxim simulator. HFSS adroitly extracts any and all discontinuities in a high-speed serial channel (such as PCI Express), with high-frequency effects represented as S parameters. That’s all well and good, but what is the designer to do with those S parameters? That’s where Nexxim comes in: the simulator can cascade those discontinuities, giving the designer a realistic picture of all of the parasitics in a given signal path.

    HFSS v10 has just shipped for the PC platform; versions for Unix/Linux are coming soon. This latest revision of HFSS offers a distributed solve option. For each license you buy, you get the ability to distribute processing across 10 Linux systems. With Linux boxes getting cheaper by the minute, there’s a big time advantage to be had in leveraging distributed processing using HFSS.

    That’s about it for now from DesignCon. If you’ve stayed with me this long, thanks for reading. Watch for timely updates from next month’s Design And Test in Europe (DATE) conference from Munich.

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