Electronic Design

DDR SDRAM DIMM Interface Tackles FPGAs

The industry's first 400-Mbit/s double-data-rate (DDR) SDRAM dual-inline memory module (DIMM) interface for FPGAs was proved on Altera's Stratix and Stratix GX FPGA families.

Tested using DDR400 SDRAM DIMMs from Micron Corp., the interface enables the implementation of memory interfaces with bandwidths of up to 25.6 Gbits/s. Advanced networking, communications, storage, server systems, and similar applications require such high-speed transfers.

Designers often face many challenges when building high-speed memory interfaces, mainly due to the need to shift the distributed queuing system (DQS) signal by 90° during the read operation. The built-in DQS phase-shift circuitry found only in Altera's FPGAs eliminates the need to use less efficient design techniques, which involve varying signal trace lengths, adding fixed delay elements (dramatically complicating board design), or others that complicate memory interface design.

In addition to the DQS phase-shift, the Stratix and Stratix GX devices have features that are essential for building reliable, high-speed memory interfaces. They include six registers in the I/O element for high-speed DDR signaling, stub-series-terminated logic (SSTL) I/O standard support for interfacing with DDR SDRAMs, feature-rich phase-locked loops for efficient clock management, and a robust clock distribution network for minimizing skew between clock and data channels.

Altera Corp.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.