The FPGA Mezzanine Card (FMC) standard has been widely adopted to provide a way to customize FPGA boards using third-party modules. Its high-speed interface can handle bandwidths needed by the latest FPGAs, but sometimes applications push even those limits.
Curtiss-Wright Controls and Tektronix have combined to exceed these limits starting with Curtiss-Wright’s CHAMP-WB-DRFM (see the figure) and Tektronix’s TADF-4300 FMC module. But the TADF-4300 FMC is not a typical FMC module. It covers two FMC sites and adds proprietary expansion sockets to utilize the full bandwidth of the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) on the FMC module and provide data to the host Xilinx Virtex-7 FPGA.
The additional sockets support 20 serializers/deserializaers (SERDES) that can operate at speeds up to 10.3 Gbits/s. There are 16 low-voltage differential signaling (LVDS) pairs on the socket in addition to the standard interface on the regular FMC sockets.
The 6U OpenVPX (VITA 65) board can handle the 12.5-Gsample/s data stream from the FMC module. Backplane communication includes Gen 2 Serial RapidIO (SRIO) support, but the Virtex-7 can be programmed to handle other fabrics as well.
The board is available with an X690T or X980T Virtex-7 FPGA that has access to 8 Gbytes of dual banked DDR3L SDRAM. The system supports Xilinx ChipScope Pro and JTAG debug interfaces. The board has thermal and power monitoring support. The VITA67.2 coax backplane option is available (see “VITA 66 And 67 Bring Fiber And RF Connectivity To VITA Standards Specs”).
The combination targets demanding, rugged applications such as electronic warfare, radar, signal intelligence (SIGINT), and electronic countermeasures (ECM). The FMC can handle dual-channel, 8-bit ADC and 10-bit DAC operation at 6.25 Gsamples/s. The frequency conversion blocks of the ADC and DAC can be extended to 70 GHz with 5 GHz of real-time bandwidth.
The TADF-4300 is based on Tektronix’s SiGe-based (silicon germanium) data converters. It supports sampling in the second Nyquist zone. Also, it allows the ADC to analyze signals up to 8 GHz and provides sub-30-ns latency for the ADC. The DAC operates at sub-10-ns rates. The spurious free dynamic range (SFDR) varies over frequency. It surpasses 58 dB up to 3 GHz and decreases to 45 dB above 3 GHz. The effective number of bits (ENOB) varies linearly from 7.2 bits at low frequencies to 6.5 bits at 3 GHz and 6.2 bits at 6 GHz.
The module exposes the reference clock on the backplane for multichannel synchronization support, allowing multiple board/module combinations to be connected into a more powerful system. The ADC has built-in calibration. The DAC doesn’t need user calibration. The FMC module uses less than 40 W.