Over the past few years, die stacking has emerged as a powerful tool for satisfying challenging IC packaging requirements. Integrating chips vertically in a single package multiplies the amount of silicon that can be crammed in a given package footprint, conserving pc-board real estate. At the same time, it enables shorter routing of interconnects from chip to chip, which speeds signalling between them. Another benefit is the simplification of surface-mount pc-board assembly because fewer components must be placed on the board.
Initial applications of die stacking, also called chip stacking, were two-chip memory combinations such as flash and SRAM. Even today, memory stacks remain popular and include new variations like flash plus flash. But chip stacking has been extended beyond memories to logic and analog ICs in packages that may also contain surface-mount passives.
In addition, chip stacking has evolved to include three- or four-die stacks and side-by-side combinations of stacked and unstacked dies within a package. The dies are typically mounted to a substrate, which is bumped to create either a chip scale package (CSP) or ball grid array (BGA) as the final package.
Though chip stacking began with mounting smaller dies onto larger ones to enable wirebonding of both, packaging vendors have developed techniques for stacking same-size die or for stacking a larger die on top of a smaller one. These variations have helped expand the number of stacked-die package options, creating whole portfolios of what vendors commonly call 3-D packages. A variety of these are now in high-volume production (Fig. 1).
Depending on the level of functional integration, 3-D packages may also be classified as systems-in-packages (SIPs). Using chip stacking to build SIPs can dramatically reduce the footprint of an unstacked, multichip design and enhance electrical performance.
A design example provided by Advanced Semiconductor Engineering (ASE) illustrates the mechanical and electrical advantages of converting a Mini-PC card with 2.4-GHz RF, logic, and DSP chips to a stacked-die multichip module in a BGA. The Mini-PC card design occupies an area of 3225 mm2 versus just 729 mm2 for the stacked-chip BGA. Plus, due to the reductions in interconnect path from logic to DSP, the crosstalk, delay, and inductance control are all improved dramatically (Fig. 2).
The viability of stacked-die packaging greatly depends on the availability of known good die (KGD). That's because the stacked-die packages' manufacturing yields will be a function of the yields of the die being packaged. Naturally, if yields are low, cost will be high. For semiconductor package assembly companies that manufacture stacked-die packages, a critical issue is whether the KGDs can be obtained in wafer form.
The package manufacturers need the die in wafer form so they can thin the wafers (through backgrinding and polishing) to the very shallow thicknesses (several mils) required for die stacking. Therefore, the chip-stacking process must begin with either high-yielding wafers, or those that have been supplied with a wafer map identifying the bad dies, so they may be discarded.
For some devices, like lower-capacity NOR flash memory, it's possible to obtain KGDs in a wafer. But for other chips, KGDs aren't readily available at the wafer level. Examples include SDRAM, DSPs, and baseband processors. Often these die are large, expensive, and difficult to source. So the economics of integrating them within stacked-die packages aren't good. For these reasons, semiconductor packaging companies have been developing an alternative form of 3-D integration, package stacking, that eliminates KGD concerns and provides another path to SIP.
Underlying Technologies: Advances in chip-stacking techniques are enabling the stacking of more dies within a package of a given height, while also placing the same number of dies into a lower-profile package. To accomplish these basic goals, packaging companies must develop a variety of underlying technologies. In terms of die processing, the key elements are wafer thinning, thin-wafer handling, and thin-die attach.
Nevertheless, chip stacking imposes special requirements on wirebonding and flip-chip assembly as well. At the package level, there's a need to source and develop thin substrates and low-profile, fine-pitch BGAs too.
Wafer thinning involves a combination of traditional backgrinding with a polishing step to remove the stresses put into the chip during backgrinding. These techniques currently produce dies that are just 100 to 150 µm thick, depending on the vendor and the wafer size. Amkor Technology and ChipPAC are both thinning 200-mm diameter wafers to the 100-µm level, while ASE is achieving 140 µm on these wafers. Meanwhile, ChipPAC also thins 300-mm diameter wafers to 150 µm thick in production.
But the future of die stacking lies with even thinner wafers. ChipPac and ASE expect to produce 200-mm wafers with 75-µm thicknesses by the end of the year, while Amkor forecasts 300-mm wafers in 76-µm thickness. Moreover, both ChipPAC and Amkor indicate that 50-µm wafers will be ready by the end of next year for 300-mm wafers.
Wafer handling presents problems that stem from the inherent weakness of thinned wafers. At a 100-µm thickness, a 200-mm wafer can no longer support itself. For 300-mm wafers, the same effect occurs at 150 µm. As long as the wafer is processed inline where it sits on a membrane, supported by a frame, handling poses no problem.
Yet when the wafer must be moved physically from one process or machine to another, wafer handling becomes an issue. Moreover, it becomes more difficult as the wafers get progressively thinner, and handling 300-mm wafers is more demanding than 200-mm wafers. As a result, wafer handling is a critical skill for vendors doing die stacking.
A related task is the ability to attach thin wafers to each other and—more critically—to the substrate, where differences in the coefficient of temperature expansion can threaten the package's mechanical reliability. Die attach is performed with a dispensed paste epoxy, or a preformed tape epoxy applied to the back of the wafer before sawing. The tape epoxy is particularly important in attaching very thin wafers.
Wirebonding is another critical capability. While standard wirebonding might have a loop height of 150 to 175 µm, die stacking could require loop heights under 100 µm.
Stacking different-size dies is another core capability. Traditionally, chip stacking was carried out with dies of different sizes so the top die was always smaller than the bottom die to permit wirebonding of both. Today, it's common to see the stacking of same-size dies or a larger die over a smaller one. Customers could then mix and match dies more easily than if only same-size dies can be used.
One way to accommodate a larger or same-size die on top is to place a spacer (a dummy piece of silicon) between the two. Then, the spacer lifts the top die just enough to allow wirebonding to the bottom die. Yet the larger the overhang on the top and the thinner the die, the harder it becomes to wirebond to the top die. But because of the customer's need for flexibility in die selection, packaging companies cultivate this skill. With a die thickness of 120 µm, ChipPAC can wirebond on a 2-mm overhang. The company also lays claim to a special process for creating die-to-die wirebonds.
As 300-mm wafers become more prevalent, another issue will arise, notes Marcos Karnezos, chief technical officer at ChipPAC. Some of these wafers are being developed with low-k dielectrics in lieu of silicon dioxide, and copper interconnects instead of aluminum. Made from organic materials, the low-k dielectrics are softer than the inorganic silicon dioxide, changing the physical requirements for wirebonding. So too does the need for wirebonding to copper die attach pads. This represents a future challenge for package manufacturers doing chip stacking.
Despite the emphasis on wirebonding-only constructions, wirebonding techniques are being used in combination with flip-chip assembly to reduce interconnect paths and stack height. Valtronic, a specialist in extreme package miniaturization, has created a process called flip-chip-on-chip (FCOC) that mates two IC dies pad-to-pad. Application of this technique can create a multidie stack (Fig. 3).
This approach eliminates the need to connect each die to the package substrate. But FCOC also demands that one of the dies be an ASIC, so that its die attach pads can be configured to accommodate both flip-chip connections to the top die and wirebonds to the substrate.
The company has developed a "repadding" technique as a way around the ASIC requirement. It adds a layer of metallization and a layer of passivation to a standard die so it may be used in lieu of a custom IC in an FCOC arrangement. This method allows back-to-back stacking of standard die and redistribution of pads to create better layouts for other flip-chip and chip-on-board designs. Moreover, it may be implemented for mounting surface-mount technology (SMT) components like an 0402- or 0201-size passive directly on the die!
Beyond wirebonds and flip-chip interconnect, chip stacking demands attention to the substrate itself, which contributes to package height and influences the number of dies that may be stacked. Vendors need to work with their suppliers to obtain thin substrates. Typically the substrate consists of a two- or four-layer laminate built on a BT core. A two-layer laminate may be sufficient for stacking memory, while four layers might be necessary to stack DSPs or ASICs. Some cases even need six layers. Core thickness and the number of laminate layers determine the overall substrate thickness.
Core thickness is currently at 80 to 100 µm, with corresponding substrate thicknesses of 190 to 210 µm for a two-layer laminate. By the start of next year, though, 60-µm cores should be available, reducing substrate thickness from 210 to 160 µm. Replacing the BT core with a polyimide tape cuts the dimensions in half. Tapes are available with 75-, 50-, and 25-µm thicknesses. Substrates constructed with these achieve thicknesses of 100, 75, and 50 µm, respectively.
How High A Stack? From a technical point of view, just how many dies can be stacked depends on the thickness of the final package and the thickness of each layer within the package. These include the substrate, die, spacers (if required), and BGA ball diameter. Substrate thickness is in turn influenced by the number of chip I/Os, which determines the number of substrate layers necessary. BGA ball diameter follows BGA ball pitch. As a result, ball diameter ranges from 0.75 mm for 1.27-mm pitch down to 0.2 mm for the extreme 0.35-mm pitch.
BGA packages come in a range of sizes. Package heights could even be 2.23 mm for a standard BGA, though much thinner profiles became common for portable applications like cell phones. In the past, 1.4 mm was the standard for stacked-chip packages in these applications. Now demand is shifting to 1.2- and 1.0-mm high packages, and even 0.8 mm is a possibility.
As a ballpark figure, it's currently possible to build three- and four-die stacks in 1.4-mm packages. As die thickness decreases to 50 µm, that number could increase. Yet as the number of dies increases, the yield decreases. Then again, it also is difficult to source KGD. These are two major motivations for package stacking.
While package stacking increases material costs per package and overall package height, it provides higher yields per stacked device, which lowers cost. According to DPAC Technologies, which offers package stacking but not die stacking, the use of known-good packaged devices leads to manufacturing yields in excess of 97%. The company has stacked as many as eight packages in a single device. But over 95% of its demand is for two-chip stacks.
In general, package stacking becomes a more attractive alternative to die stacking as the number of die and cost per die increase. But ultimately, application specifics will determine whether package stacking holds greater benefits than die stacking. One vendor, Amkor Technology, which offers die and package stacking, has developed a total-cost estimation tool that evaluates the two approaches based on die cost and yield, package cost and yield, and test inputs.
In memory applications, package stacking can also be used to obtain the desired capacity at a reasonable cost. Kevin Perry, vice president of sales and marketing at DPAC Technologies, cites a memory module for a server. Presently, a standard DIMM holds 18 512-Mbit SDRAM chips for a maximum of 1 Gbyte. Consider some hypothetical price comparisons that would justify chip stacking.
Assume that a 512-Mbit SDRAM sells for approximately $75 to $100 per chip, while a 256-Mbit SDRAM runs about $12. If stacking two 256-Mbit ICs costs around $6 to $8, then a two-chip stack equivalent of a 512-Mbit chip would be about $30. Consequently, building the 1-Gbyte DIMM with stacked 256-Mbit chips would effectively save $45 to $70 per 512-Mbit chip.
Thermal issues are another reason for package stacking. In the past, graphics processors and memories have been integrated within multichip modules. But lately, the processor's power dissipation has risen to 3 W or higher, making it necessary to heatsink the chip. That requirement complicates attempts to stack processor and memory chips.
On the other hand, graphics processors come in thermally enhanced packages that lend themselves to package stacking. Moreover, the DRAM or graphics RAM meant to be stacked with the processor probably isn't available as KGD at the wafer level, while known-good packaged versions are around.
Package stacking needs thin, flat, high-temperature, moisture-resistant packages to handle the multiple reflows and rework associated with SMT. So far, it has been applied in production only to leadframe packages like TSOPs. However, vendors like Amkor have been developing processes to stack CSPs and BGAs to achieve higher I/O counts. Amkor is currently qualifying a package-stacking process based on its etCSP package (Fig. 4). Production of the new process is expected next year. Future applications of etCSP may combine die stacking with package stacking.
Meanwhile, DPAC Technologies' CS-Stack technology stacks two fine-pitch ball grid arrays (FBGAs). The FBGA addresses both the electrical and mechanical requirements of advanced SDRAM and DDR SDRAM. As FBGA-packaged DDR memories start to become available in the next six to nine months, DPAC expects to begin production of CS-Stack components.
|Need More Information?|
Lee Smith, [email protected]
Bill Chen, (408) 986-6519
Marcos Karnezos, (510) 979-8208
Kevin Perry, (714) 898-0007
Gary Pinkerton, (888) 291-9422, ext. 20