Electronic Design

Digital Design Tip: Avoid Clusters Of High-Frequency Outputs

One of the many issues FPGA and ASIC designers must now consider before system integration is simultaneous switching output noise (SSO or SSN). Generated by too many closely spaced outputs switching simultaneously, SSN can cause a system or IC to fail. In the end, since you probably don't have control over several key parameters, you should break large high-speed buses into bytes and spread the bytes out as much as feasible.

Determining if SSN will wreak havoc on your system involves the calculation of several system-and component-level parameters. First, you must determine the total inductance, which can be calculated using the following pc-board system parameters:

  • Board thickness
  • Via diameter
  • Pad to via breakout length
  • Breakout width
  • Other pc-board parasitic inductance
  • Socket inductance.

Next, you will need to know the FPGA-or ASIC-specific parametersfor the connected satellite components, including:

  • Maximum input low voltage threshold
  • Maximum input undershoot
  • Maximum allowed ground bounce
  • Maximum load capacitance per device
  • Number and type of nets with similar load characteristics
  • Number of power and ground pins per area, region, or bank
  • Number and type of drivers used
  • Number of SSOs allowed per power and ground pin pair.

If you're designing with an FPGA, you should be able to gather or request this information and the appropriate calculations. If you're building an ASIC, you may need to research this information and create your own calculations based on simulations. Many of these parameters aren't known at design time, forcing an educated guess and erring on the side of caution.

You can submit your useful digital design and debug tips to [email protected].

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