Although the ASIC headlines the marquee as a system-on-a-chip (SoC) solution, field-programmable gate arrays (FPGAs) are pushing hard to grab that spotlight. A fast turnaround capability, coupled with the ability to modify the design should system requirements change, could make that happen.
The latest chips being sampled by Actel, Altera, Lattice Semiconductor, and Xilinx all boast gate counts well past the 1 million mark. Not too far behind is QuickLogic, which also offers several SoC solutions, but with available gate counts peaking at about a quarter-million. The largest devices come from Altera and Xilinx. Both have SRAM-based FPGAs with more than 3 million gates for the largest devices. Each company is working on still larger FPGAs. Chips approaching 6 million gates are on the drawing boards.
The SRAM-based reprogrammable approaches offered by Altera and Xilinx provide most of the resources necessary to implement a complete system. The chips pack lots of gates, a sizable amount of SRAM, and dedicated embedded processors, such as the ARM 922T for the Altera Excalibur FPGA family and the PowerPC for the Xilinx Virtex II family. Soft-core processor IP can be configured as part of the programmable logic. With capacities of 3 million gates and hundreds of kilobits of memory, these chips can swallow up a significant portion of the system logic.
However, SRAM-based solutions aren't the only routes taken by FPGA suppliers. Flash-based devices like those from Actel and Lattice Semiconductor and one-time programmable antifuse solutions from Actel and QuickLogic provide designers with alternatives. Flash-based devices eliminate the need for a separate configuration memory or a configuration code download from a host system. This becomes more important as a method to protect the intellectual property (IP) configured in the FPGAs. With external configuration memories or host downloads, the configuration data stream could be intercepted and reverse-engineered, allowing competitors to steal the IP. Thus, popularity continues to grow for flash and antifuse technologies as a means to protect the secret sauce.
To offer more of a system solution, FPGA suppliers are adding features like multiple phase-locked loops to provide flexible system timing. Then to provide higher-bandwidth input/output capabilities, they're integrating high-speed serializer-deserializers that can transfer data at speeds of up to 3.125 Gbits/s. Such speeds would allow the chips to implement 10-Gbit Sonet or Ethernet interfaces and other high-speed data transfers. To break into the high-end signal-processing arena, QuickLogic licensed the array processor architecture from PACT and will incorporate that into a family of FPGAs. Moreover, the company crafted a chip dubbed QuickMIPS. It combines about 75-k ASIC gates of configurable logic; a MIPS 4kc 32-bit processor with data and instruction caches; a 10/100-Mbit/s Ethernet media access controller; a memory controller; a PCI 32-bit interface that can run at 33 or 66 MHz; 16 kbytes of SRAM; and other resources.
ASIC vendors can now incorporate blocks of FPGA logic on the ASICs that they produce. By incorporating some FPGA logic on an ASIC, designers can complete the physical design of the chip before logic design is finished, cutting valuable time from the manufacturing cycle. This becomes quite a bonus, particularly when specifications are in flux due to changes in standards or shifting market conditions. Currently, Atmel and LSI Logic can integrate blocks of programmable logic into customer-defined chips, and Actel has a program for crafting custom programmable solutions.
>ADDITIONAL SECURITY FEATURES will be included on FPGAs to prevent the pirating of intellectual property by tapping into the configuration bit stream that is typically uploaded into the FPGA when power is turned on. This becomes more critical as increasingly larger FPGAs are able to hold more of the proprietary customer-developed IP.
>FPGA CHIP GATE COUNTS WILL EXPLODE, at least doubling today's high of about 3 million by early 2004. As the gate counts increase, the FPGAs will be able to incorporate more of the complex functions that the systems will employ.
>MORE HIGH-SPEED SERIAL PORTS will be integrated on the FPGAs to improve data-transfer bandwidth. At the same time, they will help keep the number of I/O pins under control by replacing wide parallel buses with fast serial channels.
>FPGAS WILL INCORPORATE MORE PROCESSOR CORES and other complex functions, such as Ethernet interfaces, phase-locked loops, memory controllers, and full Sonet SERDES interfaces, to unburden the system designer. It makes no sense to recreate these complex but standard functions, so designers are opting to leverage IP libraries to speed their design and let them apply their expertise to the areas of the design where they can add the most value.
>PERFORMANCE WILL CONTINUE TO SOAR as feature sizes shrink. Today, on-chip complex blocks can operate at several hundred megahertz, while basic logic functions run close to 500 MHz. The next iteration will push the performance of the complex blocks past 300 MHz, and to 600 MHz and faster for basic logic gates.
>BLOCKS OF FPGA-TYPE LOGIC will become blocks of intellectual property that ASIC vendors can, in turn, incorporate into customer-defined ASICs. This will help accelerate the design and manufacturing cycle by allowing designers to send a chip to manufacturing before all the logic is defined. That will allow products to get to market faster since the last portion of the design is just a configuration pattern that can be loaded when the chip is powered on.
>MORE FPGAS WILL OFFER LOW-VOLTAGE DIFFERENTIAL-SIGNALING I/O cells to deliver signals that are less subject to noise and able to send signals over longer pc-board traces. FPGAs already offer a wide array of single-ended I/O cells, but as I/O signaling rates continue to increase, differential I/O cells will permit signals of up to about 800 MHz.
>THE OPERATING VOLTAGES OF FPGAS will continue to fall as feature sizes shrink. Today's leading-edge FPGAs currently use a 1.5-V internal core operating voltage. That level will drop to about 1.1 V by late 2003 as chips transition from 0.13- to 0.09-µm design rules. The lower voltages will also help keep the power dissipation under control as operating speeds and the number of gates per chip hit new highs.
>INTELLECTUAL PROPERTY LIBRARIES supported by FPGA suppliers and third-party core suppliers will continue to swell as customers demand more support to re-duce their design overheads. Some dedicated on-chip resources such as CPU cores and SERDES blocks will deliver performance levels that soft-IP blocks cannot achieve.
>LOWER-COMPLEXITY FPGAS WILL GO MAINSTREAM as true ASIC replacements thanks to new architectures that will reduce chip complexity and shrink the chip area while still providing sufficient logic resources to meet system demands. That will allow the chips to be price-competitive with ASICs, even in large volumes.